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ARM: fix VCVT decoding

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UNPRED was reported instead of UNDEF

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183608 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Amaury de la Vieuville 2013-06-08 13:29:11 +00:00
parent 2dce4f27ef
commit c64835b0c5
2 changed files with 10 additions and 2 deletions
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4
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -4441,7 +4441,7 @@ static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
} }
if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); if (!(imm & 0x20)) return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
@ -4469,7 +4469,7 @@ static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
} }
if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); if (!(imm & 0x20)) return MCDisassembler::Fail;
if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;

8
test/MC/Disassembler/ARM/invalid-VCVT-arm.txt Normal file
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@ -0,0 +1,8 @@
# A8.8.307: VCVT (between floating-point and fixed-point, AdvSIMD)
# imm6=0b0xxxxx -> UNDEFINED
# RUN: echo "0x1e 0xcf 0x92 0xf3" | llvm-mc -disassemble -triple armv7 2>&1 | FileCheck %s
# RUN: echo "0x3e 0xcf 0x92 0xf3" | llvm-mc -disassemble -triple armv7 2>&1 | FileCheck %s
# CHECK: invalid instruction encoding