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[ARM64] Properly support both apple and standard syntax for FMOV

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205896 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bradley Smith
2014-04-09 14:44:49 +00:00
parent cb9ca905e3
commit c669ad900d
4 changed files with 19 additions and 13 deletions
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21
lib/Target/ARM64/ARM64InstrFormats.td
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@@ -3277,8 +3277,10 @@ class BaseUnscaledConversion<bits<2> rmode, bits<3> opcode,
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
class BaseUnscaledConversionToHigh<bits<2> rmode, bits<3> opcode, class BaseUnscaledConversionToHigh<bits<2> rmode, bits<3> opcode,
RegisterClass srcType, RegisterOperand dstType, string asm> RegisterClass srcType, RegisterOperand dstType, string asm,
: I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd[1], $Rn", "", []>, string kind>
: I<(outs dstType:$Rd), (ins srcType:$Rn), asm,
"{\t$Rd"#kind#"[1], $Rn|"#kind#"\t$Rd[1], $Rn}", "", []>,
Sched<[WriteFCopy]> { Sched<[WriteFCopy]> {
bits<5> Rd; bits<5> Rd;
bits<5> Rn; bits<5> Rn;
@@ -3293,8 +3295,10 @@ class BaseUnscaledConversionToHigh<bits<2> rmode, bits<3> opcode,
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
class BaseUnscaledConversionFromHigh<bits<2> rmode, bits<3> opcode, class BaseUnscaledConversionFromHigh<bits<2> rmode, bits<3> opcode,
RegisterOperand srcType, RegisterClass dstType, string asm> RegisterOperand srcType, RegisterClass dstType, string asm,
: I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn[1]", "", []>, string kind>
: I<(outs dstType:$Rd), (ins srcType:$Rn), asm,
"{\t$Rd, $Rn"#kind#"[1]|"#kind#"\t$Rd, $Rn[1]}", "", []>,
Sched<[WriteFCopy]> { Sched<[WriteFCopy]> {
bits<5> Rd; bits<5> Rd;
bits<5> Rn; bits<5> Rn;
@@ -3331,21 +3335,16 @@ multiclass UnscaledConversion<string asm> {
} }
def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128, def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
asm#".d"> { asm, ".d"> {
let Inst{31} = 1; let Inst{31} = 1;
let Inst{22} = 0; let Inst{22} = 0;
} }
def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64, def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
asm#".d"> { asm, ".d"> {
let Inst{31} = 1; let Inst{31} = 1;
let Inst{22} = 0; let Inst{22} = 0;
} }
def : InstAlias<asm#"$Vd.d[1], $Rn",
(!cast<Instruction>(NAME#XDHighr) V128:$Vd, GPR64:$Rn), 0>;
def : InstAlias<asm#"$Rd, $Vn.d[1]",
(!cast<Instruction>(NAME#DXHighr) GPR64:$Rd, V128:$Vn), 0>;
} }
//--- //---

2
test/MC/ARM64/fp-encoding.s
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@@ -1,4 +1,4 @@
; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding -output-asm-variant=1 < %s | FileCheck %s
foo: foo:
;----------------------------------------------------------------------------- ;-----------------------------------------------------------------------------

7
test/MC/Disassembler/ARM64/non-apple-fmov.txt Normal file
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@@ -0,0 +1,7 @@
# RUN: llvm-mc -triple arm64 -disassemble < %s | FileCheck %s
0x00 0x00 0xae 0x9e
0x00 0x00 0xaf 0x9e
# CHECK: fmov x0, v0.d[1]
# CHECK: fmov v0.d[1], x0

2
test/MC/Disassembler/ARM64/scalar-fp.txt
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@@ -1,4 +1,4 @@
# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s # RUN: llvm-mc -triple arm64-apple-darwin --disassemble -output-asm-variant=1 < %s | FileCheck %s
#----------------------------------------------------------------------------- #-----------------------------------------------------------------------------
# Floating-point arithmetic # Floating-point arithmetic