mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Thumb2 assembly parsing and encoding for LDC/STC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
18ad76bb9a
commit
c66e7afcf2
@ -3444,106 +3444,95 @@ def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Coprocessor load/store -- for disassembly only
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// Coprocessor load/store -- for disassembly only
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//
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//
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class T2CI<dag oops, dag iops, string opc, string asm>
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class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm>
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: T2I<oops, iops, NoItinerary, opc, asm, []> {
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: T2I<oops, iops, NoItinerary, opc, asm, []> {
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let Inst{31-28} = op31_28;
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let Inst{27-25} = 0b110;
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let Inst{27-25} = 0b110;
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}
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}
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multiclass T2LdStCop<bits<4> op31_28, bit load, string opc> {
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multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> {
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def _OFFSET : T2CI<(outs),
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def _OFFSET : T2CI<op31_28,
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(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
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(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
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opc, "\tp$cop, cr$CRd, $addr"> {
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asm, "\t$cop, $CRd, $addr"> {
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let Inst{31-28} = op31_28;
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bits<13> addr;
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bits<4> cop;
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bits<4> CRd;
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let Inst{24} = 1; // P = 1
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let Inst{24} = 1; // P = 1
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let Inst{23} = addr{8};
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let Inst{22} = Dbit;
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let Inst{21} = 0; // W = 0
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let Inst{21} = 0; // W = 0
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let Inst{22} = 0; // D = 0
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let Inst{20} = load;
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let Inst{20} = load;
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let Inst{19-16} = addr{12-9};
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let Inst{15-12} = CRd;
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let Inst{11-8} = cop;
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let Inst{7-0} = addr{7-0};
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let DecoderMethod = "DecodeCopMemInstruction";
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let DecoderMethod = "DecodeCopMemInstruction";
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}
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}
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def _PRE : T2CI<op31_28,
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def _PRE : T2CI<(outs),
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(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
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(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
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asm, "\t$cop, $CRd, $addr!"> {
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opc, "\tp$cop, cr$CRd, $addr!"> {
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bits<13> addr;
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let Inst{31-28} = op31_28;
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bits<4> cop;
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bits<4> CRd;
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let Inst{24} = 1; // P = 1
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let Inst{24} = 1; // P = 1
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let Inst{23} = addr{8};
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let Inst{22} = Dbit;
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let Inst{21} = 1; // W = 1
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let Inst{21} = 1; // W = 1
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let Inst{22} = 0; // D = 0
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let Inst{20} = load;
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let Inst{20} = load;
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let Inst{19-16} = addr{12-9};
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let Inst{15-12} = CRd;
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let Inst{11-8} = cop;
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let Inst{7-0} = addr{7-0};
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let DecoderMethod = "DecodeCopMemInstruction";
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let DecoderMethod = "DecodeCopMemInstruction";
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}
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}
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def _POST: T2CI<op31_28,
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def _POST : T2CI<(outs),
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(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
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(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
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postidx_imm8s4:$offset),
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opc, "\tp$cop, cr$CRd, $addr"> {
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asm, "\t$cop, $CRd, $addr, $offset"> {
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let Inst{31-28} = op31_28;
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bits<9> offset;
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bits<4> addr;
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bits<4> cop;
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bits<4> CRd;
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let Inst{24} = 0; // P = 0
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let Inst{24} = 0; // P = 0
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let Inst{23} = offset{8};
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let Inst{22} = Dbit;
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let Inst{21} = 1; // W = 1
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let Inst{21} = 1; // W = 1
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let Inst{22} = 0; // D = 0
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let Inst{20} = load;
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let Inst{20} = load;
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let Inst{19-16} = addr;
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let Inst{15-12} = CRd;
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let Inst{11-8} = cop;
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let Inst{7-0} = offset{7-0};
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let DecoderMethod = "DecodeCopMemInstruction";
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let DecoderMethod = "DecodeCopMemInstruction";
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}
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}
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def _OPTION : T2CI<op31_28, (outs),
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def _OPTION : T2CI<(outs),
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(ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
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(ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
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coproc_option_imm:$option),
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opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
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asm, "\t$cop, $CRd, $addr, $option"> {
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let Inst{31-28} = op31_28;
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bits<8> option;
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bits<4> addr;
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bits<4> cop;
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bits<4> CRd;
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let Inst{24} = 0; // P = 0
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let Inst{24} = 0; // P = 0
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let Inst{23} = 1; // U = 1
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let Inst{23} = 1; // U = 1
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let Inst{22} = Dbit;
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let Inst{21} = 0; // W = 0
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let Inst{21} = 0; // W = 0
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let Inst{22} = 0; // D = 0
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let Inst{20} = load;
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let DecoderMethod = "DecodeCopMemInstruction";
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}
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def L_OFFSET : T2CI<(outs),
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(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
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!strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
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let Inst{31-28} = op31_28;
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let Inst{24} = 1; // P = 1
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let Inst{21} = 0; // W = 0
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let Inst{22} = 1; // D = 1
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let Inst{20} = load;
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let DecoderMethod = "DecodeCopMemInstruction";
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}
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def L_PRE : T2CI<(outs),
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(ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
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!strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
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let Inst{31-28} = op31_28;
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let Inst{24} = 1; // P = 1
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let Inst{21} = 1; // W = 1
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let Inst{22} = 1; // D = 1
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let Inst{20} = load;
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let DecoderMethod = "DecodeCopMemInstruction";
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}
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def L_POST : T2CI<(outs),
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(ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr,
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postidx_imm8s4:$offset),
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!strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr, $offset"> {
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let Inst{31-28} = op31_28;
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let Inst{24} = 0; // P = 0
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let Inst{21} = 1; // W = 1
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let Inst{22} = 1; // D = 1
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let Inst{20} = load;
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let DecoderMethod = "DecodeCopMemInstruction";
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}
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def L_OPTION : T2CI<(outs),
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(ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
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!strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
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let Inst{31-28} = op31_28;
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let Inst{24} = 0; // P = 0
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let Inst{23} = 1; // U = 1
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let Inst{21} = 0; // W = 0
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let Inst{22} = 1; // D = 1
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let Inst{20} = load;
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let Inst{20} = load;
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let Inst{19-16} = addr;
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let Inst{15-12} = CRd;
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let Inst{11-8} = cop;
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let Inst{7-0} = option;
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let DecoderMethod = "DecodeCopMemInstruction";
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let DecoderMethod = "DecodeCopMemInstruction";
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}
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}
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}
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}
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defm t2LDC : T2LdStCop<0b1111, 1, "ldc">;
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defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">;
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defm t2STC : T2LdStCop<0b1111, 0, "stc">;
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defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">;
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defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">;
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defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">;
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defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">;
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defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">;
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defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">;
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defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -2086,7 +2086,8 @@ ARMAsmParser::OperandMatchResultTy ARMAsmParser::
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parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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SMLoc S = Parser.getTok().getLoc();
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SMLoc S = Parser.getTok().getLoc();
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const AsmToken &Tok = Parser.getTok();
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const AsmToken &Tok = Parser.getTok();
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assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
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if (Tok.isNot(AsmToken::Identifier))
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return MatchOperand_NoMatch;
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int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
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int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
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if (Num == -1)
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if (Num == -1)
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@ -2104,7 +2105,8 @@ ARMAsmParser::OperandMatchResultTy ARMAsmParser::
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parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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SMLoc S = Parser.getTok().getLoc();
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SMLoc S = Parser.getTok().getLoc();
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const AsmToken &Tok = Parser.getTok();
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const AsmToken &Tok = Parser.getTok();
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assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
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if (Tok.isNot(AsmToken::Identifier))
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return MatchOperand_NoMatch;
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int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
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int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
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if (Reg == -1)
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if (Reg == -1)
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@ -1244,34 +1244,60 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
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idx_mode = ARMII::IndexModePost;
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idx_mode = ARMII::IndexModePost;
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switch (Inst.getOpcode()) {
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switch (Inst.getOpcode()) {
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case ARM::LDCL_POST:
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case ARM::t2LDC2_OFFSET:
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case ARM::STCL_POST:
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case ARM::t2LDC2L_OFFSET:
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case ARM::t2LDCL_POST:
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case ARM::t2LDC2_PRE:
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case ARM::t2STCL_POST:
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case ARM::t2LDC2L_PRE:
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case ARM::t2LDC2_POST:
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case ARM::t2LDC2L_POST:
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case ARM::t2STC2_OFFSET:
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case ARM::t2STC2L_OFFSET:
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case ARM::t2STC2_PRE:
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case ARM::t2STC2L_PRE:
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case ARM::t2STC2_POST:
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case ARM::t2STC2L_POST:
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case ARM::LDC2_OFFSET:
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case ARM::LDC2L_OFFSET:
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case ARM::LDC2_PRE:
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case ARM::LDC2L_PRE:
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case ARM::LDC2_POST:
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case ARM::LDC2L_POST:
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case ARM::LDC2L_POST:
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case ARM::STC2_OFFSET:
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case ARM::STC2L_OFFSET:
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case ARM::STC2_PRE:
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case ARM::STC2L_PRE:
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case ARM::STC2_POST:
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case ARM::STC2L_POST:
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case ARM::STC2L_POST:
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case ARM::t2LDC_OFFSET:
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case ARM::t2LDCL_OFFSET:
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case ARM::t2LDC_PRE:
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case ARM::t2LDCL_PRE:
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case ARM::t2LDC_POST:
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case ARM::t2LDCL_POST:
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case ARM::t2STC_OFFSET:
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case ARM::t2STCL_OFFSET:
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case ARM::t2STC_PRE:
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case ARM::t2STCL_PRE:
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case ARM::t2STC_POST:
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case ARM::t2STCL_POST:
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case ARM::LDC_OFFSET:
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case ARM::LDCL_OFFSET:
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case ARM::LDC_PRE:
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case ARM::LDCL_PRE:
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case ARM::LDC_POST:
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case ARM::LDCL_POST:
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case ARM::STC_OFFSET:
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case ARM::STCL_OFFSET:
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case ARM::STC_PRE:
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case ARM::STCL_PRE:
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case ARM::STC_POST:
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case ARM::STCL_POST:
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imm |= U << 8;
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imm |= U << 8;
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case ARM::LDC_OPTION:
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// fall through.
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case ARM::LDCL_OPTION:
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case ARM::LDC2_OPTION:
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case ARM::LDC2L_OPTION:
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case ARM::STC_OPTION:
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case ARM::STCL_OPTION:
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case ARM::STC2_OPTION:
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case ARM::STC2L_OPTION:
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case ARM::t2LDC_OPTION:
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case ARM::t2LDCL_OPTION:
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case ARM::t2STC_OPTION:
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case ARM::t2STCL_OPTION:
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Inst.addOperand(MCOperand::CreateImm(imm));
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break;
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default:
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default:
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if (U)
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// The 'option' variant doesn't encode 'U' in the immediate since
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Inst.addOperand(MCOperand::CreateImm(
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// the immediate is unsigned [0,255].
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ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
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Inst.addOperand(MCOperand::CreateImm(imm));
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else
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Inst.addOperand(MCOperand::CreateImm(
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ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
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break;
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break;
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}
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}
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@ -494,6 +494,66 @@ _func:
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@ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d]
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@ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d]
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@------------------------------------------------------------------------------
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@ LDC{L}/LDC2{L}
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@------------------------------------------------------------------------------
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ldc2 p0, c8, [r1, #4]
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ldc2 p1, c7, [r2]
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ldc2 p2, c6, [r3, #-224]
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ldc2 p3, c5, [r4, #-120]!
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ldc2 p4, c4, [r5], #16
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ldc2 p5, c3, [r6], #-72
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ldc2l p6, c2, [r7, #4]
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ldc2l p7, c1, [r8]
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ldc2l p8, c0, [r9, #-224]
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ldc2l p9, c1, [r10, #-120]!
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ldc2l p10, c2, [r11], #16
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ldc2l p11, c3, [r12], #-72
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ldc p12, c4, [r0, #4]
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ldc p13, c5, [r1]
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ldc p14, c6, [r2, #-224]
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ldc p15, c7, [r3, #-120]!
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ldc p5, c8, [r4], #16
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ldc p4, c9, [r5], #-72
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ldcl p3, c10, [r6, #4]
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ldcl p2, c11, [r7]
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ldcl p1, c12, [r8, #-224]
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ldcl p0, c13, [r9, #-120]!
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ldcl p6, c14, [r10], #16
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ldcl p7, c15, [r11], #-72
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ldc2 p2, c8, [r1], { 25 }
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@ CHECK: ldc2 p0, c8, [r1, #4] @ encoding: [0x91,0xfd,0x01,0x80]
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||||||
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@ CHECK: ldc2 p1, c7, [r2] @ encoding: [0x92,0xfd,0x00,0x71]
|
||||||
|
@ CHECK: ldc2 p2, c6, [r3, #-224] @ encoding: [0x13,0xfd,0x38,0x62]
|
||||||
|
@ CHECK: ldc2 p3, c5, [r4, #-120]! @ encoding: [0x34,0xfd,0x1e,0x53]
|
||||||
|
@ CHECK: ldc2 p4, c4, [r5], #16 @ encoding: [0xb5,0xfc,0x04,0x44]
|
||||||
|
@ CHECK: ldc2 p5, c3, [r6], #-72 @ encoding: [0x36,0xfc,0x12,0x35]
|
||||||
|
@ CHECK: ldc2l p6, c2, [r7, #4] @ encoding: [0xd7,0xfd,0x01,0x26]
|
||||||
|
@ CHECK: ldc2l p7, c1, [r8] @ encoding: [0xd8,0xfd,0x00,0x17]
|
||||||
|
@ CHECK: ldc2l p8, c0, [r9, #-224] @ encoding: [0x59,0xfd,0x38,0x08]
|
||||||
|
@ CHECK: ldc2l p9, c1, [r10, #-120]! @ encoding: [0x7a,0xfd,0x1e,0x19]
|
||||||
|
@ CHECK: ldc2l p10, c2, [r11], #16 @ encoding: [0xfb,0xfc,0x04,0x2a]
|
||||||
|
@ CHECK: ldc2l p11, c3, [r12], #-72 @ encoding: [0x7c,0xfc,0x12,0x3b]
|
||||||
|
|
||||||
|
@ CHECK: ldc p12, c4, [r0, #4] @ encoding: [0x90,0xed,0x01,0x4c]
|
||||||
|
@ CHECK: ldc p13, c5, [r1] @ encoding: [0x91,0xed,0x00,0x5d]
|
||||||
|
@ CHECK: ldc p14, c6, [r2, #-224] @ encoding: [0x12,0xed,0x38,0x6e]
|
||||||
|
@ CHECK: ldc p15, c7, [r3, #-120]! @ encoding: [0x33,0xed,0x1e,0x7f]
|
||||||
|
@ CHECK: ldc p5, c8, [r4], #16 @ encoding: [0xb4,0xec,0x04,0x85]
|
||||||
|
@ CHECK: ldc p4, c9, [r5], #-72 @ encoding: [0x35,0xec,0x12,0x94]
|
||||||
|
@ CHECK: ldcl p3, c10, [r6, #4] @ encoding: [0xd6,0xed,0x01,0xa3]
|
||||||
|
@ CHECK: ldcl p2, c11, [r7] @ encoding: [0xd7,0xed,0x00,0xb2]
|
||||||
|
@ CHECK: ldcl p1, c12, [r8, #-224] @ encoding: [0x58,0xed,0x38,0xc1]
|
||||||
|
@ CHECK: ldcl p0, c13, [r9, #-120]! @ encoding: [0x79,0xed,0x1e,0xd0]
|
||||||
|
@ CHECK: ldcl p6, c14, [r10], #16 @ encoding: [0xfa,0xec,0x04,0xe6]
|
||||||
|
@ CHECK: ldcl p7, c15, [r11], #-72 @ encoding: [0x7b,0xec,0x12,0xf7]
|
||||||
|
|
||||||
|
@ CHECK: ldc2 p2, c8, [r1], {25} @ encoding: [0x91,0xfc,0x19,0x82]
|
||||||
|
|
||||||
|
|
||||||
@------------------------------------------------------------------------------
|
@------------------------------------------------------------------------------
|
||||||
@ LDMIA
|
@ LDMIA
|
||||||
@------------------------------------------------------------------------------
|
@------------------------------------------------------------------------------
|
||||||
@ -2122,6 +2182,66 @@ _func:
|
|||||||
@ CHECK: ssub8eq r5, r1, r2 @ encoding: [0xc1,0xfa,0x02,0xf5]
|
@ CHECK: ssub8eq r5, r1, r2 @ encoding: [0xc1,0xfa,0x02,0xf5]
|
||||||
|
|
||||||
|
|
||||||
|
@------------------------------------------------------------------------------
|
||||||
|
@ STC{L}/STC2{L}
|
||||||
|
@------------------------------------------------------------------------------
|
||||||
|
stc2 p0, c8, [r1, #4]
|
||||||
|
stc2 p1, c7, [r2]
|
||||||
|
stc2 p2, c6, [r3, #-224]
|
||||||
|
stc2 p3, c5, [r4, #-120]!
|
||||||
|
stc2 p4, c4, [r5], #16
|
||||||
|
stc2 p5, c3, [r6], #-72
|
||||||
|
stc2l p6, c2, [r7, #4]
|
||||||
|
stc2l p7, c1, [r8]
|
||||||
|
stc2l p8, c0, [r9, #-224]
|
||||||
|
stc2l p9, c1, [r10, #-120]!
|
||||||
|
stc2l p10, c2, [r11], #16
|
||||||
|
stc2l p11, c3, [r12], #-72
|
||||||
|
|
||||||
|
stc p12, c4, [r0, #4]
|
||||||
|
stc p13, c5, [r1]
|
||||||
|
stc p14, c6, [r2, #-224]
|
||||||
|
stc p15, c7, [r3, #-120]!
|
||||||
|
stc p5, c8, [r4], #16
|
||||||
|
stc p4, c9, [r5], #-72
|
||||||
|
stcl p3, c10, [r6, #4]
|
||||||
|
stcl p2, c11, [r7]
|
||||||
|
stcl p1, c12, [r8, #-224]
|
||||||
|
stcl p0, c13, [r9, #-120]!
|
||||||
|
stcl p6, c14, [r10], #16
|
||||||
|
stcl p7, c15, [r11], #-72
|
||||||
|
|
||||||
|
stc2 p2, c8, [r1], { 25 }
|
||||||
|
|
||||||
|
@ CHECK: stc2 p0, c8, [r1, #4] @ encoding: [0x81,0xfd,0x01,0x80]
|
||||||
|
@ CHECK: stc2 p1, c7, [r2] @ encoding: [0x82,0xfd,0x00,0x71]
|
||||||
|
@ CHECK: stc2 p2, c6, [r3, #-224] @ encoding: [0x03,0xfd,0x38,0x62]
|
||||||
|
@ CHECK: stc2 p3, c5, [r4, #-120]! @ encoding: [0x24,0xfd,0x1e,0x53]
|
||||||
|
@ CHECK: stc2 p4, c4, [r5], #16 @ encoding: [0xa5,0xfc,0x04,0x44]
|
||||||
|
@ CHECK: stc2 p5, c3, [r6], #-72 @ encoding: [0x26,0xfc,0x12,0x35]
|
||||||
|
@ CHECK: stc2l p6, c2, [r7, #4] @ encoding: [0xc7,0xfd,0x01,0x26]
|
||||||
|
@ CHECK: stc2l p7, c1, [r8] @ encoding: [0xc8,0xfd,0x00,0x17]
|
||||||
|
@ CHECK: stc2l p8, c0, [r9, #-224] @ encoding: [0x49,0xfd,0x38,0x08]
|
||||||
|
@ CHECK: stc2l p9, c1, [r10, #-120]! @ encoding: [0x6a,0xfd,0x1e,0x19]
|
||||||
|
@ CHECK: stc2l p10, c2, [r11], #16 @ encoding: [0xeb,0xfc,0x04,0x2a]
|
||||||
|
@ CHECK: stc2l p11, c3, [r12], #-72 @ encoding: [0x6c,0xfc,0x12,0x3b]
|
||||||
|
|
||||||
|
@ CHECK: stc p12, c4, [r0, #4] @ encoding: [0x80,0xed,0x01,0x4c]
|
||||||
|
@ CHECK: stc p13, c5, [r1] @ encoding: [0x81,0xed,0x00,0x5d]
|
||||||
|
@ CHECK: stc p14, c6, [r2, #-224] @ encoding: [0x02,0xed,0x38,0x6e]
|
||||||
|
@ CHECK: stc p15, c7, [r3, #-120]! @ encoding: [0x23,0xed,0x1e,0x7f]
|
||||||
|
@ CHECK: stc p5, c8, [r4], #16 @ encoding: [0xa4,0xec,0x04,0x85]
|
||||||
|
@ CHECK: stc p4, c9, [r5], #-72 @ encoding: [0x25,0xec,0x12,0x94]
|
||||||
|
@ CHECK: stcl p3, c10, [r6, #4] @ encoding: [0xc6,0xed,0x01,0xa3]
|
||||||
|
@ CHECK: stcl p2, c11, [r7] @ encoding: [0xc7,0xed,0x00,0xb2]
|
||||||
|
@ CHECK: stcl p1, c12, [r8, #-224] @ encoding: [0x48,0xed,0x38,0xc1]
|
||||||
|
@ CHECK: stcl p0, c13, [r9, #-120]! @ encoding: [0x69,0xed,0x1e,0xd0]
|
||||||
|
@ CHECK: stcl p6, c14, [r10], #16 @ encoding: [0xea,0xec,0x04,0xe6]
|
||||||
|
@ CHECK: stcl p7, c15, [r11], #-72 @ encoding: [0x6b,0xec,0x12,0xf7]
|
||||||
|
|
||||||
|
@ CHECK: stc2 p2, c8, [r1], {25} @ encoding: [0x81,0xfc,0x19,0x82]
|
||||||
|
|
||||||
|
|
||||||
@------------------------------------------------------------------------------
|
@------------------------------------------------------------------------------
|
||||||
@ STMIA
|
@ STMIA
|
||||||
@------------------------------------------------------------------------------
|
@------------------------------------------------------------------------------
|
||||||
|
|||||||
@ -218,7 +218,7 @@
|
|||||||
# CHECK: pld [r5, #30]
|
# CHECK: pld [r5, #30]
|
||||||
0x95 0xf8 0x1e 0xf0
|
0x95 0xf8 0x1e 0xf0
|
||||||
|
|
||||||
# CHECK: stc p12, cr15, [r9], {137}
|
# CHECK: stc2 p12, c15, [r9], {137}
|
||||||
0x89 0xfc 0x89 0xfc
|
0x89 0xfc 0x89 0xfc
|
||||||
|
|
||||||
# CHECK: vmov r1, r0, d11
|
# CHECK: vmov r1, r0, d11
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user