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R600/SI: Add missing parameter to div_fmas intrinsic

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220338 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-10-21 22:20:55 +00:00
parent 9fa8641288
commit c68710c02d
3 changed files with 9 additions and 7 deletions
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2
include/llvm/IR/IntrinsicsR600.td
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@ -52,7 +52,7 @@ def int_AMDGPU_div_scale : GCCBuiltin<"__builtin_amdgpu_div_scale">,
def int_AMDGPU_div_fmas : GCCBuiltin<"__builtin_amdgpu_div_fmas">, def int_AMDGPU_div_fmas : GCCBuiltin<"__builtin_amdgpu_div_fmas">,
Intrinsic<[llvm_anyfloat_ty], Intrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, llvm_i1_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_AMDGPU_div_fixup : GCCBuiltin<"__builtin_amdgpu_div_fixup">, def int_AMDGPU_div_fixup : GCCBuiltin<"__builtin_amdgpu_div_fixup">,

2
lib/Target/R600/AMDGPUISelLowering.cpp
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@ -844,6 +844,8 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
} }
case Intrinsic::AMDGPU_div_fmas: case Intrinsic::AMDGPU_div_fmas:
// FIXME: Dropping bool parameter. Work is needed to support the implicit
// read from VCC.
return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT, return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));

12
test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll
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@ -1,7 +1,7 @@
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
declare float @llvm.AMDGPU.div.fmas.f32(float, float, float) nounwind readnone declare float @llvm.AMDGPU.div.fmas.f32(float, float, float, i1) nounwind readnone
declare double @llvm.AMDGPU.div.fmas.f64(double, double, double) nounwind readnone declare double @llvm.AMDGPU.div.fmas.f64(double, double, double, i1) nounwind readnone
; SI-LABEL: {{^}}test_div_fmas_f32: ; SI-LABEL: {{^}}test_div_fmas_f32:
; SI-DAG: S_LOAD_DWORD [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SI-DAG: S_LOAD_DWORD [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
@ -12,16 +12,16 @@ declare double @llvm.AMDGPU.div.fmas.f64(double, double, double) nounwind readno
; SI: V_DIV_FMAS_F32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]] ; SI: V_DIV_FMAS_F32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]]
; SI: BUFFER_STORE_DWORD [[RESULT]], ; SI: BUFFER_STORE_DWORD [[RESULT]],
; SI: S_ENDPGM ; SI: S_ENDPGM
define void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { define void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
%result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c) nounwind readnone %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone
store float %result, float addrspace(1)* %out, align 4 store float %result, float addrspace(1)* %out, align 4
ret void ret void
} }
; SI-LABEL: {{^}}test_div_fmas_f64: ; SI-LABEL: {{^}}test_div_fmas_f64:
; SI: V_DIV_FMAS_F64 ; SI: V_DIV_FMAS_F64
define void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c) nounwind { define void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind {
%result = call double @llvm.AMDGPU.div.fmas.f64(double %a, double %b, double %c) nounwind readnone %result = call double @llvm.AMDGPU.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone
store double %result, double addrspace(1)* %out, align 8 store double %result, double addrspace(1)* %out, align 8
ret void ret void
} }