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Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable to
hopefully forestall similar errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35362 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -47,10 +47,10 @@ class RegScavenger {
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///
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///
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const TargetRegisterClass *ScavengedRC;
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const TargetRegisterClass *ScavengedRC;
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/// RegStates - The current state of all the physical registers immediately
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/// RegsAvailable - The current state of all the physical registers immediately
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/// before MBBI. One bit per physical register. If bit is set that means it's
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/// before MBBI. One bit per physical register. If bit is set that means it's
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/// available, unset means the register is currently being used.
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/// available, unset means the register is currently being used.
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BitVector RegStates;
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BitVector RegsAvailable;
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public:
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public:
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RegScavenger()
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RegScavenger()
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@@ -88,18 +88,18 @@ public:
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/// isUsed / isUsed - Test if a register is currently being used.
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/// isUsed / isUsed - Test if a register is currently being used.
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///
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///
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bool isUsed(unsigned Reg) const { return !RegStates[Reg]; }
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bool isUsed(unsigned Reg) const { return !RegsAvailable[Reg]; }
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bool isUnused(unsigned Reg) const { return RegStates[Reg]; }
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bool isUnused(unsigned Reg) const { return RegsAvailable[Reg]; }
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/// getRegsUsed - return all registers currently in use in used.
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/// getRegsUsed - return all registers currently in use in used.
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void getRegsUsed(BitVector &used, bool includeReserved);
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void getRegsUsed(BitVector &used, bool includeReserved);
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/// setUsed / setUnused - Mark the state of one or a number of registers.
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/// setUsed / setUnused - Mark the state of one or a number of registers.
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///
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///
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void setUsed(unsigned Reg) { RegStates.reset(Reg); }
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void setUsed(unsigned Reg) { RegsAvailable.reset(Reg); }
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void setUsed(BitVector Regs) { RegStates &= ~Regs; }
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void setUsed(BitVector Regs) { RegsAvailable &= ~Regs; }
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void setUnused(unsigned Reg) { RegStates.set(Reg); }
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void setUnused(unsigned Reg) { RegsAvailable.set(Reg); }
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void setUnused(BitVector Regs) { RegStates |= Regs; }
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void setUnused(BitVector Regs) { RegsAvailable |= Regs; }
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/// FindUnusedReg - Find a unused register of the specified register class
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/// FindUnusedReg - Find a unused register of the specified register class
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/// from the specified set of registers. It return 0 is none is found.
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/// from the specified set of registers. It return 0 is none is found.
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@@ -36,7 +36,7 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
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if (!MBB) {
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if (!MBB) {
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NumPhysRegs = RegInfo->getNumRegs();
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NumPhysRegs = RegInfo->getNumRegs();
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RegStates.resize(NumPhysRegs);
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RegsAvailable.resize(NumPhysRegs);
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// Create reserved registers bitvector.
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// Create reserved registers bitvector.
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ReservedRegs = RegInfo->getReservedRegs(MF);
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ReservedRegs = RegInfo->getReservedRegs(MF);
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@@ -54,10 +54,10 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
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ScavengedRC = NULL;
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ScavengedRC = NULL;
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// All registers started out unused.
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// All registers started out unused.
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RegStates.set();
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RegsAvailable.set();
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// Reserved registers are always used.
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// Reserved registers are always used.
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RegStates ^= ReservedRegs;
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RegsAvailable ^= ReservedRegs;
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// Live-in registers are in use.
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// Live-in registers are in use.
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if (!MBB->livein_empty())
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if (!MBB->livein_empty())
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@@ -182,9 +182,9 @@ void RegScavenger::backward() {
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void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
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void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
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if (includeReserved)
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if (includeReserved)
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used = RegStates;
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used = ~RegsAvailable;
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else
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else
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used = RegStates & ~ReservedRegs;
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used = ~RegsAvailable & ~ReservedRegs;
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}
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}
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/// CreateRegClassMask - Set the bits that represent the registers in the
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/// CreateRegClassMask - Set the bits that represent the registers in the
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@@ -198,32 +198,32 @@ static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
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unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
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unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
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const BitVector &Candidates) const {
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const BitVector &Candidates) const {
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// Mask off the registers which are not in the TargetRegisterClass.
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// Mask off the registers which are not in the TargetRegisterClass.
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BitVector RegStatesCopy(NumPhysRegs, false);
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BitVector RegsAvailableCopy(NumPhysRegs, false);
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CreateRegClassMask(RegClass, RegStatesCopy);
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CreateRegClassMask(RegClass, RegsAvailableCopy);
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RegStatesCopy &= RegStates;
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RegsAvailableCopy &= RegsAvailable;
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// Restrict the search to candidates.
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// Restrict the search to candidates.
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RegStatesCopy &= Candidates;
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RegsAvailableCopy &= Candidates;
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// Returns the first unused (bit is set) register, or 0 is none is found.
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// Returns the first unused (bit is set) register, or 0 is none is found.
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int Reg = RegStatesCopy.find_first();
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int Reg = RegsAvailableCopy.find_first();
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return (Reg == -1) ? 0 : Reg;
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return (Reg == -1) ? 0 : Reg;
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}
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}
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unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
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unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
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bool ExCalleeSaved) const {
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bool ExCalleeSaved) const {
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// Mask off the registers which are not in the TargetRegisterClass.
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// Mask off the registers which are not in the TargetRegisterClass.
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BitVector RegStatesCopy(NumPhysRegs, false);
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BitVector RegsAvailableCopy(NumPhysRegs, false);
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CreateRegClassMask(RegClass, RegStatesCopy);
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CreateRegClassMask(RegClass, RegsAvailableCopy);
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RegStatesCopy &= RegStates;
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RegsAvailableCopy &= RegsAvailable;
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// If looking for a non-callee-saved register, mask off all the callee-saved
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// If looking for a non-callee-saved register, mask off all the callee-saved
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// registers.
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// registers.
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if (ExCalleeSaved)
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if (ExCalleeSaved)
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RegStatesCopy &= ~CalleeSavedRegs;
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RegsAvailableCopy &= ~CalleeSavedRegs;
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// Returns the first unused (bit is set) register, or 0 is none is found.
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// Returns the first unused (bit is set) register, or 0 is none is found.
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int Reg = RegStatesCopy.find_first();
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int Reg = RegsAvailableCopy.find_first();
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return (Reg == -1) ? 0 : Reg;
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return (Reg == -1) ? 0 : Reg;
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}
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}
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