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For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37351 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-05-29 23:34:19 +00:00
parent 2c0c51593d
commit c6f2f6fbb9
1 changed files with 4 additions and 4 deletions
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8
lib/Target/ARM/ARMInstrVFP.td
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@ -108,21 +108,21 @@ def FSTS : ASI5<(ops SPR:$src, addrmode5:$addr),
let isLoad = 1 in {
def FLDMD : AXDI5<(ops addrmode5:$addr, pred:$p, reglist:$dst1, variable_ops),
"fldm${p}${addr:submode}d ${addr:base}, $dst1",
"fldm${addr:submode}d${p} ${addr:base}, $dst1",
[]>;
def FLDMS : AXSI5<(ops addrmode5:$addr, pred:$p, reglist:$dst1, variable_ops),
"fldm${p}${addr:submode}s ${addr:base}, $dst1",
"fldm${addr:submode}s${p} ${addr:base}, $dst1",
[]>;
} // isLoad
let isStore = 1 in {
def FSTMD : AXDI5<(ops addrmode5:$addr, pred:$p, reglist:$src1, variable_ops),
"fstm${p}${addr:submode}d ${addr:base}, $src1",
"fstm${addr:submode}d${p} ${addr:base}, $src1",
[]>;
def FSTMS : AXSI5<(ops addrmode5:$addr, pred:$p, reglist:$src1, variable_ops),
"fstm${p}${addr:submode}s ${addr:base}, $src1",
"fstm${addr:submode}s${p} ${addr:base}, $src1",
[]>;
} // isStore