diff --git a/include/llvm/IR/IntrinsicsHexagon.td b/include/llvm/IR/IntrinsicsHexagon.td index ef666b4149e..6f9237e35a1 100644 --- a/include/llvm/IR/IntrinsicsHexagon.td +++ b/include/llvm/IR/IntrinsicsHexagon.td @@ -254,7 +254,7 @@ class Hexagon_qi_qiqi_Intrinsic // class Hexagon_qi_qiqiqi_Intrinsic : Hexagon_Intrinsic; // // DEF_FUNCTION_TYPE_2(SI_ftype_QIQI,BT_INT,BT_BOOL,BT_BOOL) -> @@ -434,7 +434,7 @@ class Hexagon_mem_memmemsisi_Intrinsic class Hexagon_sf_si_Intrinsic : Hexagon_Intrinsic; + [IntrNoMem, Throws]>; // // Hexagon_sf_df_Intrinsic // @@ -490,14 +490,14 @@ class Hexagon_si_df_Intrinsic class Hexagon_sf_sfsf_Intrinsic : Hexagon_Intrinsic; + [IntrNoMem, Throws]>; // -// Hexagon_qi_sfsf_Intrinsic +// Hexagon_si_sfsf_Intrinsic // -class Hexagon_qi_sfsf_Intrinsic +class Hexagon_si_sfsf_Intrinsic : Hexagon_Intrinsic; + [llvm_i32_ty], [llvm_float_ty, llvm_float_ty], + [IntrNoMem, Throws]>; // // Hexagon_si_sfsi_Intrinsic // @@ -519,7 +519,7 @@ class Hexagon_sf_sfsfsf_Intrinsic : Hexagon_Intrinsic; + [IntrNoMem, Throws]>; // // Hexagon_sf_sfsfsfqi_Intrinsic // @@ -528,7 +528,7 @@ class Hexagon_sf_sfsfsfqi_Intrinsic [llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_i32_ty], - [IntrNoMem]>; + [IntrNoMem, Throws]>; // // Hexagon_di_dididi_Intrinsic // @@ -543,7 +543,7 @@ class Hexagon_di_dididisi_Intrinsic class Hexagon_df_si_Intrinsic : Hexagon_Intrinsic; + [IntrNoMem, Throws]>; // // Hexagon_df_di_Intrinsic // @@ -571,14 +571,14 @@ class Hexagon_df_df_Intrinsic class Hexagon_df_dfdf_Intrinsic : Hexagon_Intrinsic; + [IntrNoMem, Throws]>; // -// Hexagon_qi_dfdf_Intrinsic +// Hexagon_si_dfdf_Intrinsic // -class Hexagon_qi_dfdf_Intrinsic +class Hexagon_si_dfdf_Intrinsic : Hexagon_Intrinsic; + [llvm_i32_ty], [llvm_double_ty, llvm_double_ty], + [IntrNoMem, Throws]>; // // Hexagon_si_dfsi_Intrinsic // @@ -594,7 +594,7 @@ class Hexagon_df_dfdfdf_Intrinsic : Hexagon_Intrinsic; + [IntrNoMem, Throws]>; // // Hexagon_df_dfdfdf_Intrinsic // @@ -603,7 +603,7 @@ class Hexagon_df_dfdfdfqi_Intrinsic [llvm_double_ty], [llvm_double_ty, llvm_double_ty, llvm_double_ty, llvm_i32_ty], - [IntrNoMem]>; + [IntrNoMem, Throws]>; // This one below will not be generated from iset.py. @@ -624,32 +624,32 @@ Hexagon_mem_memmemsisi_Intrinsic<"circ_ldd">; // BUILTIN_INFO(HEXAGON.C2_cmpeq,QI_ftype_SISI,2) // def int_hexagon_C2_cmpeq : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpeq">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpeq">; // // BUILTIN_INFO(HEXAGON.C2_cmpgt,QI_ftype_SISI,2) // def int_hexagon_C2_cmpgt : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpgt">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgt">; // // BUILTIN_INFO(HEXAGON.C2_cmpgtu,QI_ftype_SISI,2) // def int_hexagon_C2_cmpgtu : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpgtu">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgtu">; // // BUILTIN_INFO(HEXAGON.C2_cmpeqp,QI_ftype_DIDI,2) // def int_hexagon_C2_cmpeqp : -Hexagon_qi_didi_Intrinsic<"HEXAGON_C2_cmpeqp">; +Hexagon_si_didi_Intrinsic<"HEXAGON_C2_cmpeqp">; // // BUILTIN_INFO(HEXAGON.C2_cmpgtp,QI_ftype_DIDI,2) // def int_hexagon_C2_cmpgtp : -Hexagon_qi_didi_Intrinsic<"HEXAGON_C2_cmpgtp">; +Hexagon_si_didi_Intrinsic<"HEXAGON_C2_cmpgtp">; // // BUILTIN_INFO(HEXAGON.C2_cmpgtup,QI_ftype_DIDI,2) // def int_hexagon_C2_cmpgtup : -Hexagon_qi_didi_Intrinsic<"HEXAGON_C2_cmpgtup">; +Hexagon_si_didi_Intrinsic<"HEXAGON_C2_cmpgtup">; // // BUILTIN_INFO(HEXAGON.A4_rcmpeqi,SI_ftype_SISI,2) // @@ -674,182 +674,182 @@ Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_rcmpneq">; // BUILTIN_INFO(HEXAGON.C2_bitsset,QI_ftype_SISI,2) // def int_hexagon_C2_bitsset : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_bitsset">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_bitsset">; // // BUILTIN_INFO(HEXAGON.C2_bitsclr,QI_ftype_SISI,2) // def int_hexagon_C2_bitsclr : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_bitsclr">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_bitsclr">; // // BUILTIN_INFO(HEXAGON.C4_nbitsset,QI_ftype_SISI,2) // def int_hexagon_C4_nbitsset : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_nbitsset">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_nbitsset">; // // BUILTIN_INFO(HEXAGON.C4_nbitsclr,QI_ftype_SISI,2) // def int_hexagon_C4_nbitsclr : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_nbitsclr">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_nbitsclr">; // // BUILTIN_INFO(HEXAGON.C2_cmpeqi,QI_ftype_SISI,2) // def int_hexagon_C2_cmpeqi : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpeqi">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpeqi">; // // BUILTIN_INFO(HEXAGON.C2_cmpgti,QI_ftype_SISI,2) // def int_hexagon_C2_cmpgti : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpgti">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgti">; // // BUILTIN_INFO(HEXAGON.C2_cmpgtui,QI_ftype_SISI,2) // def int_hexagon_C2_cmpgtui : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpgtui">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgtui">; // // BUILTIN_INFO(HEXAGON.C2_cmpgei,QI_ftype_SISI,2) // def int_hexagon_C2_cmpgei : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpgei">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgei">; // // BUILTIN_INFO(HEXAGON.C2_cmpgeui,QI_ftype_SISI,2) // def int_hexagon_C2_cmpgeui : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpgeui">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgeui">; // // BUILTIN_INFO(HEXAGON.C2_cmplt,QI_ftype_SISI,2) // def int_hexagon_C2_cmplt : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmplt">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmplt">; // // BUILTIN_INFO(HEXAGON.C2_cmpltu,QI_ftype_SISI,2) // def int_hexagon_C2_cmpltu : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_cmpltu">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpltu">; // // BUILTIN_INFO(HEXAGON.C2_bitsclri,QI_ftype_SISI,2) // def int_hexagon_C2_bitsclri : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C2_bitsclri">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_bitsclri">; // // BUILTIN_INFO(HEXAGON.C4_nbitsclri,QI_ftype_SISI,2) // def int_hexagon_C4_nbitsclri : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_nbitsclri">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_nbitsclri">; // // BUILTIN_INFO(HEXAGON.C4_cmpneqi,QI_ftype_SISI,2) // def int_hexagon_C4_cmpneqi : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_cmpneqi">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmpneqi">; // // BUILTIN_INFO(HEXAGON.C4_cmpltei,QI_ftype_SISI,2) // def int_hexagon_C4_cmpltei : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_cmpltei">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmpltei">; // // BUILTIN_INFO(HEXAGON.C4_cmplteui,QI_ftype_SISI,2) // def int_hexagon_C4_cmplteui : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_cmplteui">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmplteui">; // // BUILTIN_INFO(HEXAGON.C4_cmpneq,QI_ftype_SISI,2) // def int_hexagon_C4_cmpneq : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_cmpneq">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmpneq">; // // BUILTIN_INFO(HEXAGON.C4_cmplte,QI_ftype_SISI,2) // def int_hexagon_C4_cmplte : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_cmplte">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmplte">; // // BUILTIN_INFO(HEXAGON.C4_cmplteu,QI_ftype_SISI,2) // def int_hexagon_C4_cmplteu : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_C4_cmplteu">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmplteu">; // // BUILTIN_INFO(HEXAGON.C2_and,QI_ftype_QIQI,2) // def int_hexagon_C2_and : -Hexagon_qi_qiqi_Intrinsic<"HEXAGON_C2_and">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_and">; // // BUILTIN_INFO(HEXAGON.C2_or,QI_ftype_QIQI,2) // def int_hexagon_C2_or : -Hexagon_qi_qiqi_Intrinsic<"HEXAGON_C2_or">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_or">; // // BUILTIN_INFO(HEXAGON.C2_xor,QI_ftype_QIQI,2) // def int_hexagon_C2_xor : -Hexagon_qi_qiqi_Intrinsic<"HEXAGON_C2_xor">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_xor">; // // BUILTIN_INFO(HEXAGON.C2_andn,QI_ftype_QIQI,2) // def int_hexagon_C2_andn : -Hexagon_qi_qiqi_Intrinsic<"HEXAGON_C2_andn">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_andn">; // // BUILTIN_INFO(HEXAGON.C2_not,QI_ftype_QI,1) // def int_hexagon_C2_not : -Hexagon_qi_qi_Intrinsic<"HEXAGON_C2_not">; +Hexagon_si_si_Intrinsic<"HEXAGON_C2_not">; // // BUILTIN_INFO(HEXAGON.C2_orn,QI_ftype_QIQI,2) // def int_hexagon_C2_orn : -Hexagon_qi_qiqi_Intrinsic<"HEXAGON_C2_orn">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_orn">; // // BUILTIN_INFO(HEXAGON.C4_and_and,QI_ftype_QIQIQI,3) // def int_hexagon_C4_and_and : -Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON_C4_and_and">; +Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_and_and">; // // BUILTIN_INFO(HEXAGON.C4_and_or,QI_ftype_QIQIQI,3) // def int_hexagon_C4_and_or : -Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON_C4_and_or">; +Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_and_or">; // // BUILTIN_INFO(HEXAGON.C4_or_and,QI_ftype_QIQIQI,3) // def int_hexagon_C4_or_and : -Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON_C4_or_and">; +Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_or_and">; // // BUILTIN_INFO(HEXAGON.C4_or_or,QI_ftype_QIQIQI,3) // def int_hexagon_C4_or_or : -Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON_C4_or_or">; +Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_or_or">; // // BUILTIN_INFO(HEXAGON.C4_and_andn,QI_ftype_QIQIQI,3) // def int_hexagon_C4_and_andn : -Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON_C4_and_andn">; +Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_and_andn">; // // BUILTIN_INFO(HEXAGON.C4_and_orn,QI_ftype_QIQIQI,3) // def int_hexagon_C4_and_orn : -Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON_C4_and_orn">; +Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_and_orn">; // // BUILTIN_INFO(HEXAGON.C4_or_andn,QI_ftype_QIQIQI,3) // def int_hexagon_C4_or_andn : -Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON_C4_or_andn">; +Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_or_andn">; // // BUILTIN_INFO(HEXAGON.C4_or_orn,QI_ftype_QIQIQI,3) // def int_hexagon_C4_or_orn : -Hexagon_qi_qiqiqi_Intrinsic<"HEXAGON_C4_or_orn">; +Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_or_orn">; // // BUILTIN_INFO(HEXAGON.C2_pxfer_map,QI_ftype_QI,1) // def int_hexagon_C2_pxfer_map : -Hexagon_qi_qi_Intrinsic<"HEXAGON_C2_pxfer_map">; +Hexagon_si_qi_Intrinsic<"HEXAGON_C2_pxfer_map">; // // BUILTIN_INFO(HEXAGON.C2_any8,QI_ftype_QI,1) // def int_hexagon_C2_any8 : -Hexagon_qi_qi_Intrinsic<"HEXAGON_C2_any8">; +Hexagon_si_qi_Intrinsic<"HEXAGON_C2_any8">; // // BUILTIN_INFO(HEXAGON.C2_all8,QI_ftype_QI,1) // def int_hexagon_C2_all8 : -Hexagon_qi_qi_Intrinsic<"HEXAGON_C2_all8">; +Hexagon_si_qi_Intrinsic<"HEXAGON_C2_all8">; // // BUILTIN_INFO(HEXAGON.C2_vitpack,SI_ftype_QIQI,2) // @@ -889,167 +889,167 @@ Hexagon_di_qi_Intrinsic<"HEXAGON_C2_mask">; // BUILTIN_INFO(HEXAGON.A2_vcmpbeq,QI_ftype_DIDI,2) // def int_hexagon_A2_vcmpbeq : -Hexagon_qi_didi_Intrinsic<"HEXAGON_A2_vcmpbeq">; +Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpbeq">; // // BUILTIN_INFO(HEXAGON.A4_vcmpbeqi,QI_ftype_DISI,2) // def int_hexagon_A4_vcmpbeqi : -Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmpbeqi">; +Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpbeqi">; // // BUILTIN_INFO(HEXAGON.A4_vcmpbeq_any,QI_ftype_DIDI,2) // def int_hexagon_A4_vcmpbeq_any : -Hexagon_qi_didi_Intrinsic<"HEXAGON_A4_vcmpbeq_any">; +Hexagon_si_didi_Intrinsic<"HEXAGON_A4_vcmpbeq_any">; // // BUILTIN_INFO(HEXAGON.A2_vcmpbgtu,QI_ftype_DIDI,2) // def int_hexagon_A2_vcmpbgtu : -Hexagon_qi_didi_Intrinsic<"HEXAGON_A2_vcmpbgtu">; +Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpbgtu">; // // BUILTIN_INFO(HEXAGON.A4_vcmpbgtui,QI_ftype_DISI,2) // def int_hexagon_A4_vcmpbgtui : -Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmpbgtui">; +Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpbgtui">; // // BUILTIN_INFO(HEXAGON.A4_vcmpbgt,QI_ftype_DIDI,2) // def int_hexagon_A4_vcmpbgt : -Hexagon_qi_didi_Intrinsic<"HEXAGON_A4_vcmpbgt">; +Hexagon_si_didi_Intrinsic<"HEXAGON_A4_vcmpbgt">; // // BUILTIN_INFO(HEXAGON.A4_vcmpbgti,QI_ftype_DISI,2) // def int_hexagon_A4_vcmpbgti : -Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmpbgti">; +Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpbgti">; // // BUILTIN_INFO(HEXAGON.A4_cmpbeq,QI_ftype_SISI,2) // def int_hexagon_A4_cmpbeq : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmpbeq">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbeq">; // // BUILTIN_INFO(HEXAGON.A4_cmpbeqi,QI_ftype_SISI,2) // def int_hexagon_A4_cmpbeqi : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmpbeqi">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbeqi">; // // BUILTIN_INFO(HEXAGON.A4_cmpbgtu,QI_ftype_SISI,2) // def int_hexagon_A4_cmpbgtu : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmpbgtu">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbgtu">; // // BUILTIN_INFO(HEXAGON.A4_cmpbgtui,QI_ftype_SISI,2) // def int_hexagon_A4_cmpbgtui : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmpbgtui">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbgtui">; // // BUILTIN_INFO(HEXAGON.A4_cmpbgt,QI_ftype_SISI,2) // def int_hexagon_A4_cmpbgt : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmpbgt">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbgt">; // // BUILTIN_INFO(HEXAGON.A4_cmpbgti,QI_ftype_SISI,2) // def int_hexagon_A4_cmpbgti : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmpbgti">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbgti">; // // BUILTIN_INFO(HEXAGON.A2_vcmpheq,QI_ftype_DIDI,2) // def int_hexagon_A2_vcmpheq : -Hexagon_qi_didi_Intrinsic<"HEXAGON_A2_vcmpheq">; +Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpheq">; // // BUILTIN_INFO(HEXAGON.A2_vcmphgt,QI_ftype_DIDI,2) // def int_hexagon_A2_vcmphgt : -Hexagon_qi_didi_Intrinsic<"HEXAGON_A2_vcmphgt">; +Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmphgt">; // // BUILTIN_INFO(HEXAGON.A2_vcmphgtu,QI_ftype_DIDI,2) // def int_hexagon_A2_vcmphgtu : -Hexagon_qi_didi_Intrinsic<"HEXAGON_A2_vcmphgtu">; +Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmphgtu">; // // BUILTIN_INFO(HEXAGON.A4_vcmpheqi,QI_ftype_DISI,2) // def int_hexagon_A4_vcmpheqi : -Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmpheqi">; +Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpheqi">; // // BUILTIN_INFO(HEXAGON.A4_vcmphgti,QI_ftype_DISI,2) // def int_hexagon_A4_vcmphgti : -Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmphgti">; +Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmphgti">; // // BUILTIN_INFO(HEXAGON.A4_vcmphgtui,QI_ftype_DISI,2) // def int_hexagon_A4_vcmphgtui : -Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmphgtui">; +Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmphgtui">; // // BUILTIN_INFO(HEXAGON.A4_cmpheq,QI_ftype_SISI,2) // def int_hexagon_A4_cmpheq : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmpheq">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpheq">; // // BUILTIN_INFO(HEXAGON.A4_cmphgt,QI_ftype_SISI,2) // def int_hexagon_A4_cmphgt : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmphgt">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmphgt">; // // BUILTIN_INFO(HEXAGON.A4_cmphgtu,QI_ftype_SISI,2) // def int_hexagon_A4_cmphgtu : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmphgtu">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmphgtu">; // // BUILTIN_INFO(HEXAGON.A4_cmpheqi,QI_ftype_SISI,2) // def int_hexagon_A4_cmpheqi : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmpheqi">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpheqi">; // // BUILTIN_INFO(HEXAGON.A4_cmphgti,QI_ftype_SISI,2) // def int_hexagon_A4_cmphgti : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmphgti">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmphgti">; // // BUILTIN_INFO(HEXAGON.A4_cmphgtui,QI_ftype_SISI,2) // def int_hexagon_A4_cmphgtui : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_A4_cmphgtui">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmphgtui">; // // BUILTIN_INFO(HEXAGON.A2_vcmpweq,QI_ftype_DIDI,2) // def int_hexagon_A2_vcmpweq : -Hexagon_qi_didi_Intrinsic<"HEXAGON_A2_vcmpweq">; +Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpweq">; // // BUILTIN_INFO(HEXAGON.A2_vcmpwgt,QI_ftype_DIDI,2) // def int_hexagon_A2_vcmpwgt : -Hexagon_qi_didi_Intrinsic<"HEXAGON_A2_vcmpwgt">; +Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpwgt">; // // BUILTIN_INFO(HEXAGON.A2_vcmpwgtu,QI_ftype_DIDI,2) // def int_hexagon_A2_vcmpwgtu : -Hexagon_qi_didi_Intrinsic<"HEXAGON_A2_vcmpwgtu">; +Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpwgtu">; // // BUILTIN_INFO(HEXAGON.A4_vcmpweqi,QI_ftype_DISI,2) // def int_hexagon_A4_vcmpweqi : -Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmpweqi">; +Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpweqi">; // // BUILTIN_INFO(HEXAGON.A4_vcmpwgti,QI_ftype_DISI,2) // def int_hexagon_A4_vcmpwgti : -Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmpwgti">; +Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpwgti">; // // BUILTIN_INFO(HEXAGON.A4_vcmpwgtui,QI_ftype_DISI,2) // def int_hexagon_A4_vcmpwgtui : -Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_vcmpwgtui">; +Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpwgtui">; // // BUILTIN_INFO(HEXAGON.A4_boundscheck,QI_ftype_SIDI,2) // def int_hexagon_A4_boundscheck : -Hexagon_qi_sidi_Intrinsic<"HEXAGON_A4_boundscheck">; +Hexagon_si_sidi_Intrinsic<"HEXAGON_A4_boundscheck">; // // BUILTIN_INFO(HEXAGON.A4_tlbmatch,QI_ftype_DISI,2) // def int_hexagon_A4_tlbmatch : -Hexagon_qi_disi_Intrinsic<"HEXAGON_A4_tlbmatch">; +Hexagon_si_disi_Intrinsic<"HEXAGON_A4_tlbmatch">; // // BUILTIN_INFO(HEXAGON.C2_tfrpr,SI_ftype_QI,1) // @@ -1059,17 +1059,17 @@ Hexagon_si_qi_Intrinsic<"HEXAGON_C2_tfrpr">; // BUILTIN_INFO(HEXAGON.C2_tfrrp,QI_ftype_SI,1) // def int_hexagon_C2_tfrrp : -Hexagon_qi_si_Intrinsic<"HEXAGON_C2_tfrrp">; +Hexagon_si_si_Intrinsic<"HEXAGON_C2_tfrrp">; // // BUILTIN_INFO(HEXAGON.C4_fastcorner9,QI_ftype_QIQI,2) // def int_hexagon_C4_fastcorner9 : -Hexagon_qi_qiqi_Intrinsic<"HEXAGON_C4_fastcorner9">; +Hexagon_si_qiqi_Intrinsic<"HEXAGON_C4_fastcorner9">; // // BUILTIN_INFO(HEXAGON.C4_fastcorner9_not,QI_ftype_QIQI,2) // def int_hexagon_C4_fastcorner9_not : -Hexagon_qi_qiqi_Intrinsic<"HEXAGON_C4_fastcorner9_not">; +Hexagon_si_qiqi_Intrinsic<"HEXAGON_C4_fastcorner9_not">; // // BUILTIN_INFO(HEXAGON.M2_mpy_acc_hh_s0,SI_ftype_SISISI,3) // @@ -2849,7 +2849,7 @@ Hexagon_di_di_Intrinsic<"HEXAGON_A2_tfrp">; // BUILTIN_INFO(HEXAGON.A2_tfrpi,DI_ftype_SI,1) // def int_hexagon_A2_tfrpi : -Hexagon_di_si_Intrinsic<"HEXAGON_A2_tfrpi">; +Hexagon_di_di_Intrinsic<"HEXAGON_A2_tfrpi">; // // BUILTIN_INFO(HEXAGON.A2_zxtb,SI_ftype_SI,1) // @@ -3609,22 +3609,22 @@ Hexagon_sf_sfsfsf_Intrinsic<"HEXAGON_F2_sffms_lib">; // BUILTIN_INFO(HEXAGON.F2_sfcmpeq,QI_ftype_SFSF,2) // def int_hexagon_F2_sfcmpeq : -Hexagon_qi_sfsf_Intrinsic<"HEXAGON_F2_sfcmpeq">; +Hexagon_si_sfsf_Intrinsic<"HEXAGON_F2_sfcmpeq">; // // BUILTIN_INFO(HEXAGON.F2_sfcmpgt,QI_ftype_SFSF,2) // def int_hexagon_F2_sfcmpgt : -Hexagon_qi_sfsf_Intrinsic<"HEXAGON_F2_sfcmpgt">; +Hexagon_si_sfsf_Intrinsic<"HEXAGON_F2_sfcmpgt">; // // BUILTIN_INFO(HEXAGON.F2_sfcmpge,QI_ftype_SFSF,2) // def int_hexagon_F2_sfcmpge : -Hexagon_qi_sfsf_Intrinsic<"HEXAGON_F2_sfcmpge">; +Hexagon_si_sfsf_Intrinsic<"HEXAGON_F2_sfcmpge">; // // BUILTIN_INFO(HEXAGON.F2_sfcmpuo,QI_ftype_SFSF,2) // def int_hexagon_F2_sfcmpuo : -Hexagon_qi_sfsf_Intrinsic<"HEXAGON_F2_sfcmpuo">; +Hexagon_si_sfsf_Intrinsic<"HEXAGON_F2_sfcmpuo">; // // BUILTIN_INFO(HEXAGON.F2_sfmax,SF_ftype_SFSF,2) // @@ -3669,22 +3669,22 @@ Hexagon_sf_sf_Intrinsic<"HEXAGON_F2_sffixupr">; // BUILTIN_INFO(HEXAGON.F2_dfcmpeq,QI_ftype_DFDF,2) // def int_hexagon_F2_dfcmpeq : -Hexagon_qi_dfdf_Intrinsic<"HEXAGON_F2_dfcmpeq">; +Hexagon_si_dfdf_Intrinsic<"HEXAGON_F2_dfcmpeq">; // // BUILTIN_INFO(HEXAGON.F2_dfcmpgt,QI_ftype_DFDF,2) // def int_hexagon_F2_dfcmpgt : -Hexagon_qi_dfdf_Intrinsic<"HEXAGON_F2_dfcmpgt">; +Hexagon_si_dfdf_Intrinsic<"HEXAGON_F2_dfcmpgt">; // // BUILTIN_INFO(HEXAGON.F2_dfcmpge,QI_ftype_DFDF,2) // def int_hexagon_F2_dfcmpge : -Hexagon_qi_dfdf_Intrinsic<"HEXAGON_F2_dfcmpge">; +Hexagon_si_dfdf_Intrinsic<"HEXAGON_F2_dfcmpge">; // // BUILTIN_INFO(HEXAGON.F2_dfcmpuo,QI_ftype_DFDF,2) // def int_hexagon_F2_dfcmpuo : -Hexagon_qi_dfdf_Intrinsic<"HEXAGON_F2_dfcmpuo">; +Hexagon_si_dfdf_Intrinsic<"HEXAGON_F2_dfcmpuo">; // // BUILTIN_INFO(HEXAGON.F2_dfclass,QI_ftype_DFSI,2) // @@ -4429,12 +4429,12 @@ Hexagon_di_didi_Intrinsic<"HEXAGON_S2_extractup_rp">; // BUILTIN_INFO(HEXAGON.S2_tstbit_i,QI_ftype_SISI,2) // def int_hexagon_S2_tstbit_i : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_S2_tstbit_i">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_tstbit_i">; // // BUILTIN_INFO(HEXAGON.S4_ntstbit_i,QI_ftype_SISI,2) // def int_hexagon_S4_ntstbit_i : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_S4_ntstbit_i">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_ntstbit_i">; // // BUILTIN_INFO(HEXAGON.S2_setbit_i,SI_ftype_SISI,2) // @@ -4454,12 +4454,12 @@ Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_clrbit_i">; // BUILTIN_INFO(HEXAGON.S2_tstbit_r,QI_ftype_SISI,2) // def int_hexagon_S2_tstbit_r : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_S2_tstbit_r">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_tstbit_r">; // // BUILTIN_INFO(HEXAGON.S4_ntstbit_r,QI_ftype_SISI,2) // def int_hexagon_S4_ntstbit_r : -Hexagon_qi_sisi_Intrinsic<"HEXAGON_S4_ntstbit_r">; +Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_ntstbit_r">; // // BUILTIN_INFO(HEXAGON.S2_setbit_r,SI_ftype_SISI,2) // diff --git a/lib/Target/Hexagon/HexagonIntrinsics.td b/lib/Target/Hexagon/HexagonIntrinsics.td index 0ba96bc60b5..8ec3e11d77b 100644 --- a/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/lib/Target/Hexagon/HexagonIntrinsics.td @@ -135,6 +135,10 @@ class T_FF_pat : Pat<(IntID F32:$Rs, F32:$Rt), (MI F32:$Rs, F32:$Rt)>; +class T_DD_pat + : Pat<(IntID F64:$Rs, F64:$Rt), + (MI F64:$Rs, F64:$Rt)>; + class T_FFF_pat : Pat<(IntID F32:$Rs, F32:$Rt, F32:$Ru), (MI F32:$Rs, F32:$Rt, F32:$Ru)>; diff --git a/lib/Target/Hexagon/HexagonIntrinsicsV4.td b/lib/Target/Hexagon/HexagonIntrinsicsV4.td index b51adac56a5..4b1cf3f4c02 100644 --- a/lib/Target/Hexagon/HexagonIntrinsicsV4.td +++ b/lib/Target/Hexagon/HexagonIntrinsicsV4.td @@ -42,6 +42,21 @@ def: T_RR_pat; def: T_RR_pat; def: T_RI_pat; +def : T_RR_pat; +def : T_RR_pat; +def : T_RR_pat; +def : T_RR_pat; +def : T_RR_pat; +def : T_RR_pat; + +def : T_RI_pat; +def : T_RI_pat; +def : T_RI_pat; + +def : T_RI_pat; +def : T_RI_pat; +def : T_RI_pat; + def : T_RP_pat ; def : T_PR_pat; diff --git a/lib/Target/Hexagon/HexagonIntrinsicsV5.td b/lib/Target/Hexagon/HexagonIntrinsicsV5.td index b9beb301b51..b2abe962717 100644 --- a/lib/Target/Hexagon/HexagonIntrinsicsV5.td +++ b/lib/Target/Hexagon/HexagonIntrinsicsV5.td @@ -33,6 +33,17 @@ def : T_FFF_pat ; def : T_FFF_pat ; def : T_FFFQ_pat ; +// Compare floating-point value +def : T_FF_pat ; +def : T_FF_pat ; +def : T_FF_pat ; +def : T_FF_pat ; + +def : T_DD_pat ; +def : T_DD_pat ; +def : T_DD_pat ; +def : T_DD_pat ; + // Create floating-point value def : T_I_pat ; def : T_I_pat ; diff --git a/test/CodeGen/Hexagon/cmp-not.ll b/test/CodeGen/Hexagon/cmp-not.ll deleted file mode 100644 index abcddc38b23..00000000000 --- a/test/CodeGen/Hexagon/cmp-not.ll +++ /dev/null @@ -1,50 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s -; Check that we generate matching compare insn. - -; Function Attrs: nounwind -define i32 @neqi(i32 %argc) #0 { -entry: - %p = alloca i8, align 1 - %0 = tail call i1 @llvm.hexagon.C4.cmpneqi(i32 %argc, i32 512) - %conv = zext i1 %0 to i8 - store volatile i8 %conv, i8* %p, align 1 - %p.0.p.0. = load volatile i8* %p, align 1 - %conv1 = zext i8 %p.0.p.0. to i32 - ret i32 %conv1 -} -; CHECK: p{{[0-3]}}{{ *}} = !cmp.eq(r{{[0-9]+}}, ##512) - -; Function Attrs: nounwind readnone -declare i1 @llvm.hexagon.C4.cmpneqi(i32, i32) #1 - -; Function Attrs: nounwind -define i32 @ngti(i32 %argc) #0 { -entry: - %p = alloca i8, align 1 - %0 = tail call i1 @llvm.hexagon.C4.cmpltei(i32 %argc, i32 4) - %conv = zext i1 %0 to i8 - store volatile i8 %conv, i8* %p, align 1 - %p.0.p.0. = load volatile i8* %p, align 1 - %conv1 = zext i8 %p.0.p.0. to i32 - ret i32 %conv1 -} -; CHECK: p{{[0-3]}}{{ *}} = !cmp.gt(r{{[0-9]+}}, #4) - -; Function Attrs: nounwind readnone -declare i1 @llvm.hexagon.C4.cmpltei(i32, i32) #1 - -; Function Attrs: nounwind -define i32 @ngtui(i32 %argc) #0 { -entry: - %p = alloca i8, align 1 - %0 = tail call i1 @llvm.hexagon.C4.cmplteui(i32 %argc, i32 4) - %conv = zext i1 %0 to i8 - store volatile i8 %conv, i8* %p, align 1 - %p.0.p.0. = load volatile i8* %p, align 1 - %conv1 = zext i8 %p.0.p.0. to i32 - ret i32 %conv1 -} -; CHECK: p{{[0-3]}}{{ *}} = !cmp.gtu(r{{[0-9]+}}, #4) - -; Function Attrs: nounwind readnone -declare i1 @llvm.hexagon.C4.cmplteui(i32, i32) #1 diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll b/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll index f6d0025693b..aef8127d668 100644 --- a/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll +++ b/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll @@ -24,6 +24,63 @@ define i32 @F2_dfclass(double %a) { } ; CHECK: p0 = dfclass(r1:0, #0) +; Compare floating-point value +declare i32 @llvm.hexagon.F2.sfcmpge(float, float) +define i32 @F2_sfcmpge(float %a, float %b) { + %z = call i32 @llvm.hexagon.F2.sfcmpge(float %a, float %b) + ret i32 %z +} +; CHECK: p0 = sfcmp.ge(r0, r1) + +declare i32 @llvm.hexagon.F2.sfcmpuo(float, float) +define i32 @F2_sfcmpuo(float %a, float %b) { + %z = call i32 @llvm.hexagon.F2.sfcmpuo(float %a, float %b) + ret i32 %z +} +; CHECK: p0 = sfcmp.uo(r0, r1) + +declare i32 @llvm.hexagon.F2.sfcmpeq(float, float) +define i32 @F2_sfcmpeq(float %a, float %b) { + %z = call i32 @llvm.hexagon.F2.sfcmpeq(float %a, float %b) + ret i32 %z +} +; CHECK: p0 = sfcmp.eq(r0, r1) + +declare i32 @llvm.hexagon.F2.sfcmpgt(float, float) +define i32 @F2_sfcmpgt(float %a, float %b) { + %z = call i32 @llvm.hexagon.F2.sfcmpgt(float %a, float %b) + ret i32 %z +} +; CHECK: p0 = sfcmp.gt(r0, r1) + +declare i32 @llvm.hexagon.F2.dfcmpge(double, double) +define i32 @F2_dfcmpge(double %a, double %b) { + %z = call i32 @llvm.hexagon.F2.dfcmpge(double %a, double %b) + ret i32 %z +} +; CHECK: p0 = dfcmp.ge(r1:0, r3:2) + +declare i32 @llvm.hexagon.F2.dfcmpuo(double, double) +define i32 @F2_dfcmpuo(double %a, double %b) { + %z = call i32 @llvm.hexagon.F2.dfcmpuo(double %a, double %b) + ret i32 %z +} +; CHECK: p0 = dfcmp.uo(r1:0, r3:2) + +declare i32 @llvm.hexagon.F2.dfcmpeq(double, double) +define i32 @F2_dfcmpeq(double %a, double %b) { + %z = call i32 @llvm.hexagon.F2.dfcmpeq(double %a, double %b) + ret i32 %z +} +; CHECK: p0 = dfcmp.eq(r1:0, r3:2) + +declare i32 @llvm.hexagon.F2.dfcmpgt(double, double) +define i32 @F2_dfcmpgt(double %a, double %b) { + %z = call i32 @llvm.hexagon.F2.dfcmpgt(double %a, double %b) + ret i32 %z +} +; CHECK: p0 = dfcmp.gt(r1:0, r3:2) + ; Convert floating-point value to other format declare double @llvm.hexagon.F2.conv.sf2df(float) define double @F2_conv_sf2df(float %a) { diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll b/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll new file mode 100644 index 00000000000..ffedfd99908 --- /dev/null +++ b/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll @@ -0,0 +1,198 @@ +; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; Hexagon Programmer's Reference Manual 11.10.7 XTYPE/PRED + +; Compare byte +declare i32 @llvm.hexagon.A4.cmpbgt(i32, i32) +define i32 @A4_cmpbgt(i32 %a, i32 %b) { + %z = call i32 @llvm.hexagon.A4.cmpbgt(i32 %a, i32 %b) + ret i32 %z +} +; CHECK: p0 = cmpb.gt(r0, r1) + +declare i32 @llvm.hexagon.A4.cmpbeq(i32, i32) +define i32 @A4_cmpbeq(i32 %a, i32 %b) { + %z = call i32 @llvm.hexagon.A4.cmpbeq(i32 %a, i32 %b) + ret i32 %z +} +; CHECK: p0 = cmpb.eq(r0, r1) + +declare i32 @llvm.hexagon.A4.cmpbgtu(i32, i32) +define i32 @A4_cmpbgtu(i32 %a, i32 %b) { + %z = call i32 @llvm.hexagon.A4.cmpbgtu(i32 %a, i32 %b) + ret i32 %z +} +; CHECK: p0 = cmpb.gtu(r0, r1) + +declare i32 @llvm.hexagon.A4.cmpbgti(i32, i32) +define i32 @A4_cmpbgti(i32 %a) { + %z = call i32 @llvm.hexagon.A4.cmpbgti(i32 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = cmpb.gt(r0, #0) + +declare i32 @llvm.hexagon.A4.cmpbeqi(i32, i32) +define i32 @A4_cmpbeqi(i32 %a) { + %z = call i32 @llvm.hexagon.A4.cmpbeqi(i32 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = cmpb.eq(r0, #0) + +declare i32 @llvm.hexagon.A4.cmpbgtui(i32, i32) +define i32 @A4_cmpbgtui(i32 %a) { + %z = call i32 @llvm.hexagon.A4.cmpbgtui(i32 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = cmpb.gtu(r0, #0) + +; Compare half +declare i32 @llvm.hexagon.A4.cmphgt(i32, i32) +define i32 @A4_cmphgt(i32 %a, i32 %b) { + %z = call i32 @llvm.hexagon.A4.cmphgt(i32 %a, i32 %b) + ret i32 %z +} +; CHECK: p0 = cmph.gt(r0, r1) + +declare i32 @llvm.hexagon.A4.cmpheq(i32, i32) +define i32 @A4_cmpheq(i32 %a, i32 %b) { + %z = call i32 @llvm.hexagon.A4.cmpheq(i32 %a, i32 %b) + ret i32 %z +} +; CHECK: p0 = cmph.eq(r0, r1) + +declare i32 @llvm.hexagon.A4.cmphgtu(i32, i32) +define i32 @A4_cmphgtu(i32 %a, i32 %b) { + %z = call i32 @llvm.hexagon.A4.cmphgtu(i32 %a, i32 %b) + ret i32 %z +} +; CHECK: p0 = cmph.gtu(r0, r1) + +declare i32 @llvm.hexagon.A4.cmphgti(i32, i32) +define i32 @A4_cmphgti(i32 %a) { + %z = call i32 @llvm.hexagon.A4.cmphgti(i32 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = cmph.gt(r0, #0) + +declare i32 @llvm.hexagon.A4.cmpheqi(i32, i32) +define i32 @A4_cmpheqi(i32 %a) { + %z = call i32 @llvm.hexagon.A4.cmpheqi(i32 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = cmph.eq(r0, #0) + +declare i32 @llvm.hexagon.A4.cmphgtui(i32, i32) +define i32 @A4_cmphgtui(i32 %a) { + %z = call i32 @llvm.hexagon.A4.cmphgtui(i32 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = cmph.gtu(r0, #0) + +; Compare doublewords +declare i32 @llvm.hexagon.C2.cmpgtp(i64, i64) +define i32 @C2_cmpgtp(i64 %a, i64 %b) { + %z = call i32 @llvm.hexagon.C2.cmpgtp(i64 %a, i64 %b) + ret i32 %z +} +; CHECK: p0 = cmp.gt(r1:0, r3:2) + +declare i32 @llvm.hexagon.C2.cmpeqp(i64, i64) +define i32 @C2_cmpeqp(i64 %a, i64 %b) { + %z = call i32 @llvm.hexagon.C2.cmpeqp(i64 %a, i64 %b) + ret i32 %z +} +; CHECK: p0 = cmp.eq(r1:0, r3:2) + +declare i32 @llvm.hexagon.C2.cmpgtup(i64, i64) +define i32 @C2_cmpgtup(i64 %a, i64 %b) { + %z = call i32 @llvm.hexagon.C2.cmpgtup(i64 %a, i64 %b) + ret i32 %z +} +; CHECK: p0 = cmp.gtu(r1:0, r3:2) + +; Compare bitmask +declare i32 @llvm.hexagon.C2.bitsclri(i32, i32) +define i32 @C2_bitsclri(i32 %a) { + %z = call i32 @llvm.hexagon.C2.bitsclri(i32 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = bitsclr(r0, #0) + +declare i32 @llvm.hexagon.C4.nbitsclri(i32, i32) +define i32 @C4_nbitsclri(i32 %a) { + %z = call i32 @llvm.hexagon.C4.nbitsclri(i32 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = !bitsclr(r0, #0) + +declare i32 @llvm.hexagon.C2.bitsset(i32, i32) +define i32 @C2_bitsset(i32 %a, i32 %b) { + %z = call i32 @llvm.hexagon.C2.bitsset(i32 %a, i32 %b) + ret i32 %z +} +; CHECK: p0 = bitsset(r0, r1) + +declare i32 @llvm.hexagon.C4.nbitsset(i32, i32) +define i32 @C4_nbitsset(i32 %a, i32 %b) { + %z = call i32 @llvm.hexagon.C4.nbitsset(i32 %a, i32 %b) + ret i32 %z +} +; CHECK: p0 = !bitsset(r0, r1) + +declare i32 @llvm.hexagon.C2.bitsclr(i32, i32) +define i32 @C2_bitsclr(i32 %a, i32 %b) { + %z = call i32 @llvm.hexagon.C2.bitsclr(i32 %a, i32 %b) + ret i32 %z +} +; CHECK: p0 = bitsclr(r0, r1) + +declare i32 @llvm.hexagon.C4.nbitsclr(i32, i32) +define i32 @C4_nbitsclr(i32 %a, i32 %b) { + %z = call i32 @llvm.hexagon.C4.nbitsclr(i32 %a, i32 %b) + ret i32 %z +} +; CHECK: p0 = !bitsclr(r0, r1) + +; Mask generate from predicate +declare i64 @llvm.hexagon.C2.mask(i32) +define i64 @C2_mask(i32 %a) { + %z = call i64 @llvm.hexagon.C2.mask(i32 %a) + ret i64 %z +} +; CHECK: = mask(r0) + +; Check for TLB match +declare i32 @llvm.hexagon.A4.tlbmatch(i64, i32) +define i32 @A4_tlbmatch(i64 %a, i32 %b) { + %z = call i32 @llvm.hexagon.A4.tlbmatch(i64 %a, i32 %b) + ret i32 %z +} +; CHECK: p0 = tlbmatch(r1:0, r2) + +; Test bit +declare i32 @llvm.hexagon.S2.tstbit.i(i32, i32) +define i32 @S2_tstbit_i(i32 %a) { + %z = call i32 @llvm.hexagon.S2.tstbit.i(i32 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = tstbit(r0, #0) + +declare i32 @llvm.hexagon.S4.ntstbit.i(i32, i32) +define i32 @S4_ntstbit_i(i32 %a) { + %z = call i32 @llvm.hexagon.S4.ntstbit.i(i32 %a, i32 0) + ret i32 %z +} +; CHECK: p0 = !tstbit(r0, #0) + +declare i32 @llvm.hexagon.S2.tstbit.r(i32, i32) +define i32 @S2_tstbit_r(i32 %a, i32 %b) { + %z = call i32 @llvm.hexagon.S2.tstbit.r(i32 %a, i32 %b) + ret i32 %z +} +; CHECK: p0 = tstbit(r0, r1) + +declare i32 @llvm.hexagon.S4.ntstbit.r(i32, i32) +define i32 @S4_ntstbit_r(i32 %a, i32 %b) { + %z = call i32 @llvm.hexagon.S4.ntstbit.r(i32 %a, i32 %b) + ret i32 %z +} +; CHECK: p0 = !tstbit(r0, r1)