mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-01 00:33:09 +00:00
Revert r157831
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157896 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Manman Ren
parent
57ae246a6a
commit
c73ea9102b
@ -1143,9 +1143,7 @@ let Uses = [EFLAGS] in {
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0, 0>;
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}
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let isCompare = 1 in {
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defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
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}
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//===----------------------------------------------------------------------===//
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@ -33,7 +33,6 @@
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/Statistic.h"
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#include <limits>
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#define GET_INSTRINFO_CTOR
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@ -41,8 +40,6 @@
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using namespace llvm;
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STATISTIC(NumCmpsRemoved, "Number of Cmps removed due to an earlier Sub");
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static cl::opt<bool>
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NoFusing("disable-spill-fusing",
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cl::desc("Disable fusing of spill code into instructions"));
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@ -2730,326 +2727,6 @@ void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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NewMIs.push_back(MIB);
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}
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bool X86InstrInfo::
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AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
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int &CmpValue) const {
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switch (MI->getOpcode()) {
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default: break;
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case X86::CMP64ri32:
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case X86::CMP64ri8:
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case X86::CMP32ri:
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case X86::CMP32ri8:
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case X86::CMP16ri:
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case X86::CMP16ri8:
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case X86::CMP8ri:
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SrcReg = MI->getOperand(0).getReg();
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CmpMask = ~0;
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CmpValue = MI->getOperand(1).getImm();
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return true;
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case X86::CMP64rr:
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case X86::CMP32rr:
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case X86::CMP16rr:
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case X86::CMP8rr:
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SrcReg = MI->getOperand(0).getReg();
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CmpMask = ~0;
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CmpValue = 0;
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return true;
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}
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return false;
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}
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// This function updates condition code for SET Opcodes.
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// The input condition code can be E,NE,L,LE,G,GE,B,BE,A,AE and
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// the updated condition code will be E,NE,G,GE,L,LE,A,AE,B,BE.
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// This is to convert from a > b to b < a, a >= b to b <= a etc.
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static unsigned UpdateSETCondToOptimizeCmp(unsigned SETOpc) {
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switch (SETOpc) {
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default: return 0;
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case X86::SETEr: return X86::SETEr;
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case X86::SETEm: return X86::SETEm;
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case X86::SETNEr: return X86::SETNEr;
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case X86::SETNEm: return X86::SETNEm;
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case X86::SETLr: return X86::SETGr;
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case X86::SETLm: return X86::SETGm;
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case X86::SETLEr: return X86::SETGEr;
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case X86::SETLEm: return X86::SETGEm;
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case X86::SETGr: return X86::SETLr;
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case X86::SETGm: return X86::SETLm;
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case X86::SETGEr: return X86::SETLEr;
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case X86::SETGEm: return X86::SETLEm;
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case X86::SETBr: return X86::SETAr;
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case X86::SETBm: return X86::SETAm;
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case X86::SETBEr: return X86::SETAEr;
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case X86::SETBEm: return X86::SETAEm;
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case X86::SETAr: return X86::SETBr;
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case X86::SETAm: return X86::SETBm;
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case X86::SETAEr: return X86::SETBEr;
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case X86::SETAEm: return X86::SETBEm;
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}
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}
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// This function updates condition code for Branch Opcodes.
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// The input condition code can be E,NE,L,LE,G,GE,B,BE,A,AE and
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// the updated condition code will be E,NE,G,GE,L,LE,A,AE,B,BE.
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// This is to convert from a > b to b < a, a >= b to b <= a etc.
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static unsigned UpdateBranchCondToOptimizeCmp(unsigned BranchOpc) {
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switch (BranchOpc) {
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default: return 0;
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case X86::JE_4: return X86::JE_4;
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case X86::JNE_4: return X86::JNE_4;
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case X86::JL_4: return X86::JG_4;
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case X86::JLE_4: return X86::JGE_4;
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case X86::JG_4: return X86::JL_4;
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case X86::JGE_4: return X86::JLE_4;
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case X86::JB_4: return X86::JA_4;
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case X86::JBE_4: return X86::JAE_4;
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case X86::JA_4: return X86::JB_4;
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case X86::JAE_4: return X86::JBE_4;
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}
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}
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// This function updates condition code for CMOV Opcodes.
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// The input condition code can be E,NE,L,LE,G,GE,B,BE,A,AE and
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// the updated condition code will be E,NE,G,GE,L,LE,A,AE,B,BE.
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// This is to convert from a > b to b < a, a >= b to b <= a etc.
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static unsigned UpdateCMovCondToOptimizeCmp(unsigned CMovOpc) {
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switch (CMovOpc) {
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default: return 0;
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case X86::CMOVE16rm: return X86::CMOVE16rm;
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case X86::CMOVE16rr: return X86::CMOVE16rr;
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case X86::CMOVE32rm: return X86::CMOVE32rm;
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case X86::CMOVE32rr: return X86::CMOVE32rr;
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case X86::CMOVE64rm: return X86::CMOVE64rm;
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case X86::CMOVE64rr: return X86::CMOVE64rr;
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case X86::CMOVNE16rm: return X86::CMOVNE16rm;
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case X86::CMOVNE16rr: return X86::CMOVNE16rr;
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case X86::CMOVNE32rm: return X86::CMOVNE32rm;
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case X86::CMOVNE32rr: return X86::CMOVNE32rr;
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case X86::CMOVNE64rm: return X86::CMOVNE64rm;
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case X86::CMOVNE64rr: return X86::CMOVNE64rr;
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case X86::CMOVL16rm: return X86::CMOVG16rm;
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case X86::CMOVL16rr: return X86::CMOVG16rr;
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case X86::CMOVL32rm: return X86::CMOVG32rm;
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case X86::CMOVL32rr: return X86::CMOVG32rr;
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case X86::CMOVL64rm: return X86::CMOVG64rm;
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case X86::CMOVL64rr: return X86::CMOVG64rr;
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case X86::CMOVLE16rm: return X86::CMOVGE16rm;
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case X86::CMOVLE16rr: return X86::CMOVGE16rr;
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case X86::CMOVLE32rm: return X86::CMOVGE32rm;
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case X86::CMOVLE32rr: return X86::CMOVGE32rr;
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case X86::CMOVLE64rm: return X86::CMOVGE64rm;
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case X86::CMOVLE64rr: return X86::CMOVGE64rr;
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case X86::CMOVG16rm: return X86::CMOVL16rm;
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case X86::CMOVG16rr: return X86::CMOVL16rr;
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case X86::CMOVG32rm: return X86::CMOVL32rm;
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case X86::CMOVG32rr: return X86::CMOVL32rr;
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case X86::CMOVG64rm: return X86::CMOVL64rm;
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case X86::CMOVG64rr: return X86::CMOVL64rr;
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case X86::CMOVGE16rm: return X86::CMOVLE16rm;
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case X86::CMOVGE16rr: return X86::CMOVLE16rr;
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case X86::CMOVGE32rm: return X86::CMOVLE32rm;
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case X86::CMOVGE32rr: return X86::CMOVLE32rr;
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case X86::CMOVGE64rm: return X86::CMOVLE64rm;
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case X86::CMOVGE64rr: return X86::CMOVLE64rr;
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case X86::CMOVB16rm: return X86::CMOVA16rm;
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case X86::CMOVB16rr: return X86::CMOVA16rr;
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case X86::CMOVB32rm: return X86::CMOVA32rm;
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case X86::CMOVB32rr: return X86::CMOVA32rr;
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case X86::CMOVB64rm: return X86::CMOVA64rm;
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case X86::CMOVB64rr: return X86::CMOVA64rr;
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case X86::CMOVBE16rm: return X86::CMOVAE16rm;
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case X86::CMOVBE16rr: return X86::CMOVAE16rr;
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case X86::CMOVBE32rm: return X86::CMOVAE32rm;
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case X86::CMOVBE32rr: return X86::CMOVAE32rr;
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case X86::CMOVBE64rm: return X86::CMOVAE64rm;
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case X86::CMOVBE64rr: return X86::CMOVAE64rr;
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case X86::CMOVA16rm: return X86::CMOVB16rm;
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case X86::CMOVA16rr: return X86::CMOVB16rr;
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case X86::CMOVA32rm: return X86::CMOVB32rm;
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case X86::CMOVA32rr: return X86::CMOVB32rr;
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case X86::CMOVA64rm: return X86::CMOVB64rm;
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case X86::CMOVA64rr: return X86::CMOVB64rr;
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case X86::CMOVAE16rm: return X86::CMOVBE16rm;
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case X86::CMOVAE16rr: return X86::CMOVBE16rr;
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case X86::CMOVAE32rm: return X86::CMOVBE32rm;
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case X86::CMOVAE32rr: return X86::CMOVBE32rr;
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case X86::CMOVAE64rm: return X86::CMOVBE64rm;
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case X86::CMOVAE64rr: return X86::CMOVBE64rr;
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}
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}
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bool X86InstrInfo::
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OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
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int CmpValue, const MachineRegisterInfo *MRI) const {
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MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
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if (llvm::next(DI) != MRI->def_end())
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// Only support one definition.
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return false;
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MachineInstr *MI = &*DI;
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// Get ready to iterate backward from CmpInstr.
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MachineBasicBlock::iterator I = CmpInstr, E = MI,
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B = CmpInstr->getParent()->begin();
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// Early exit if CmpInstr is at the beginning of the BB.
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if (I == B) return false;
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// For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
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// For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
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MachineInstr *Sub = NULL;
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unsigned SrcReg2 = 0;
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if (CmpInstr->getOpcode() == X86::CMP64rr ||
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CmpInstr->getOpcode() == X86::CMP32rr ||
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CmpInstr->getOpcode() == X86::CMP16rr ||
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CmpInstr->getOpcode() == X86::CMP8rr) {
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SrcReg2 = CmpInstr->getOperand(1).getReg();
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}
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// Search backwards for a SUB instruction.
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// If EFLAGS is updated in the middle, we can not remove the CMP instruction.
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--I;
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for (; I != E; --I) {
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const MachineInstr &Instr = *I;
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// Check whether the current instruction is SUB(r1, r2) or SUB(r2, r1).
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if (((CmpInstr->getOpcode() == X86::CMP64rr &&
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Instr.getOpcode() == X86::SUB64rr) ||
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(CmpInstr->getOpcode() == X86::CMP32rr &&
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Instr.getOpcode() == X86::SUB32rr)||
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(CmpInstr->getOpcode() == X86::CMP16rr &&
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Instr.getOpcode() == X86::SUB16rr)||
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(CmpInstr->getOpcode() == X86::CMP8rr &&
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Instr.getOpcode() == X86::SUB8rr)) &&
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((Instr.getOperand(1).getReg() == SrcReg &&
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Instr.getOperand(2).getReg() == SrcReg2) ||
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(Instr.getOperand(1).getReg() == SrcReg2 &&
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Instr.getOperand(2).getReg() == SrcReg))) {
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Sub = &*I;
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break;
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}
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// Check whether the current instruction is SUBri(r1, CmpValue).
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if (((CmpInstr->getOpcode() == X86::CMP64ri32 &&
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Instr.getOpcode() == X86::SUB64ri32) ||
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(CmpInstr->getOpcode() == X86::CMP64ri8 &&
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Instr.getOpcode() == X86::SUB64ri8) ||
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(CmpInstr->getOpcode() == X86::CMP32ri &&
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Instr.getOpcode() == X86::SUB32ri) ||
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(CmpInstr->getOpcode() == X86::CMP32ri8 &&
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Instr.getOpcode() == X86::SUB32ri8) ||
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(CmpInstr->getOpcode() == X86::CMP16ri &&
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Instr.getOpcode() == X86::SUB16ri) ||
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(CmpInstr->getOpcode() == X86::CMP16ri8 &&
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Instr.getOpcode() == X86::SUB16ri8) ||
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(CmpInstr->getOpcode() == X86::CMP8ri &&
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Instr.getOpcode() == X86::SUB8ri)) &&
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CmpValue != 0 &&
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Instr.getOperand(1).getReg() == SrcReg &&
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Instr.getOperand(2).getImm() == CmpValue) {
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Sub = &*I;
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break;
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}
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for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
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const MachineOperand &MO = Instr.getOperand(IO);
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if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
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return false;
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if (!MO.isReg()) continue;
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// This instruction modifies or uses EFLAGS before we find a SUB.
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// We can't do this transformation.
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if (MO.getReg() == X86::EFLAGS)
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return false;
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}
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if (I == B)
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// Reaching beginning of the block.
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return false;
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}
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// Return false if no candidates exist.
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if (!Sub)
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return false;
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MI = Sub;
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switch (MI->getOpcode()) {
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default: break;
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case X86::SUB64rr:
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case X86::SUB32rr:
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case X86::SUB16rr:
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case X86::SUB8rr:
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case X86::SUB64ri32:
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case X86::SUB64ri8:
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case X86::SUB32ri:
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case X86::SUB32ri8:
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case X86::SUB16ri:
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case X86::SUB16ri8:
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case X86::SUB8ri: {
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// Scan forward from CmpInstr for the use of EFLAGS.
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// Handle the condition codes GE, L, G, LE, B, L, BE, LE.
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SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
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bool isSafe = false;
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I = CmpInstr;
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E = CmpInstr->getParent()->end();
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while (!isSafe && ++I != E) {
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const MachineInstr &Instr = *I;
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for (unsigned IO = 0, EO = Instr.getNumOperands();
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!isSafe && IO != EO; ++IO) {
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const MachineOperand &MO = Instr.getOperand(IO);
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if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) {
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isSafe = true;
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break;
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}
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if (!MO.isReg() || MO.getReg() != X86::EFLAGS)
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continue;
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// EFLAGS is redefined by this instruction.
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if (MO.isDef()) {
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isSafe = true;
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break;
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}
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// EFLAGS is used by this instruction.
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// If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
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// to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
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unsigned NewOpc = UpdateBranchCondToOptimizeCmp(Instr.getOpcode());
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if (!NewOpc) NewOpc = UpdateSETCondToOptimizeCmp(Instr.getOpcode());
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if (!NewOpc) NewOpc = UpdateCMovCondToOptimizeCmp(Instr.getOpcode());
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if (!NewOpc) return false;
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// Push the MachineInstr to OpsToUpdate.
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// If it is safe to remove CmpInstr, the condition code of these
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// instructions will be modified.
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if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
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Sub->getOperand(2).getReg() == SrcReg)
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OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
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}
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}
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// We may exit the loop at end of the basic block.
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// In that case, it is still safe to remove CmpInstr.
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// Make sure Sub instruction defines EFLAGS.
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assert(MI->getOperand(3).getReg() == X86::EFLAGS &&
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"Expected EFLAGS is the 4th operand of SUBrr or SUBri.");
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MI->getOperand(3).setIsDef(true);
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CmpInstr->eraseFromParent();
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// Modify the condition code of instructions in OpsToUpdate.
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for (unsigned i = 0; i < OpsToUpdate.size(); i++)
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OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
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NumCmpsRemoved++;
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return true;
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}
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}
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return false;
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}
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bool X86InstrInfo::
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OptimizeSubInstr(MachineInstr *SubInstr, const MachineRegisterInfo *MRI) const {
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// If destination is a memory operand, do not perform this optimization.
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@ -367,12 +367,6 @@ public:
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virtual bool OptimizeSubInstr(MachineInstr *SubInstr,
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const MachineRegisterInfo *MRI) const;
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virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
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int &CmpMask, int &CmpValue) const;
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virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
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int CmpMask, int CmpValue,
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const MachineRegisterInfo *MRI) const;
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private:
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MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
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MachineFunction::iterator &MFI,
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@ -83,25 +83,6 @@ entry:
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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; redundant cmp instruction
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define i32 @l(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: l:
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; CHECK-NOT: cmp
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%cmp = icmp slt i32 %b, %a
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%sub = sub nsw i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 %a
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ret i32 %cond
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}
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define i32 @m(i32 %a, i32 %b) nounwind {
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entry:
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||||
; CHECK: m:
|
||||
; CHECK-NOT: cmp
|
||||
%cmp = icmp sgt i32 %a, %b
|
||||
%sub = sub nsw i32 %a, %b
|
||||
%cond = select i1 %cmp, i32 %b, i32 %sub
|
||||
ret i32 %cond
|
||||
}
|
||||
; rdar://11540023
|
||||
define i64 @n(i64 %x, i64 %y) nounwind {
|
||||
entry:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user