diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index d1e84cdd4a7..b51b9d40e8e 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -127,6 +127,9 @@ def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2]>; def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>; def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2]>; +// V6M Processors. +def : Processor<"cortex-m0", ARMV6Itineraries, [ArchV6, FeatureDB]>; + // V6T2 Processors. def : Processor<"arm1156t2-s", ARMV6Itineraries, [ArchV6T2, FeatureThumb2]>; @@ -141,6 +144,8 @@ def : Processor<"cortex-a8", CortexA8Itineraries, def : Processor<"cortex-a9", CortexA9Itineraries, [ArchV7A, FeatureThumb2, FeatureNEON, FeatureT2ExtractPack, FeatureDB]>; + +// V7M Processors. def : ProcNoItin<"cortex-m3", [ArchV7M, FeatureThumb2, FeatureHWDiv, FeatureDB]>; def : ProcNoItin<"cortex-m4", [ArchV7M, FeatureThumb2, FeatureHWDiv, diff --git a/test/CodeGen/Thumb/barrier.ll b/test/CodeGen/Thumb/barrier.ll index 44a3f46a181..0081837054a 100644 --- a/test/CodeGen/Thumb/barrier.ll +++ b/test/CodeGen/Thumb/barrier.ll @@ -1,17 +1,24 @@ -; RUN: llc < %s -march=thumb -mattr=+v6 | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+v6 | FileCheck %s -check-prefix=V6 +; RUN: llc < %s -march=thumb -mcpu=cortex-m0 | FileCheck %s -check-prefix=M0 declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1 ) define void @t1() { -; CHECK: t1: -; CHECK: blx {{_*}}sync_synchronize +; V6: t1: +; V6: blx {{_*}}sync_synchronize + +; M0: t1: +; M0: dsb call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 true ) ret void } define void @t2() { -; CHECK: t2: -; CHECK: blx {{_*}}sync_synchronize +; V6: t2: +; V6: blx {{_*}}sync_synchronize + +; M0: t2: +; M0: dmb call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 false ) ret void }