6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-19 03:24:09 +00:00
Code Issues Projects Releases Wiki Activity

AVX512: combining setcc and zext is wrong on AVX512

Browse Source 
because vector compare instruction puts result in mask register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199798 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
2014-01-22 12:26:19 +00:00
parent bb96dfcf4f
commit c75a44cda7
2 changed files with 15 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -5082,9 +5082,12 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
if (N0.getOpcode() == ISD::SETCC) { if (N0.getOpcode() == ISD::SETCC) {
if (!LegalOperations && VT.isVector() && if (!LegalOperations && VT.isVector() &&
N0.getValueType().getVectorElementType() == MVT::i1) { N0.getValueType().getVectorElementType() == MVT::i1) {
EVT N0VT = N0.getOperand(0).getValueType();
if (getSetCCResultType(N0VT) == N0.getValueType())
return SDValue();
// zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
// Only do this before legalize for now. // Only do this before legalize for now.
EVT N0VT = N0.getOperand(0).getValueType();
EVT EltVT = VT.getVectorElementType(); EVT EltVT = VT.getVectorElementType();
SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
DAG.getConstant(1, EltVT)); DAG.getConstant(1, EltVT));

11
test/CodeGen/X86/avx512-vec-cmp.ll
View File

@ -122,3 +122,14 @@ define i16 @test12(<16 x i64> %a, <16 x i64> %b) nounwind {
%res1 = bitcast <16 x i1> %res to i16 %res1 = bitcast <16 x i1> %res to i16
ret i16 %res1 ret i16 %res1
} }
; CHECK-LABEL: test13
; CHECK: vcmpeqps %zmm
; CHECK: vpbroadcastd
; CHECK: ret
define <16 x i32> @test13(<16 x float>%a, <16 x float>%b)
{
%cmpvector_i = fcmp oeq <16 x float> %a, %b
%conv = zext <16 x i1> %cmpvector_i to <16 x i32>
ret <16 x i32> %conv
}