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Expand 64-bit CTLZ nodes if target architecture does not support it. Add test

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case for DCLO and DCLZ.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147022 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2011-12-21 00:20:27 +00:00
parent 7f162743fc
commit c79507a4dd
2 changed files with 22 additions and 1 deletions
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4
lib/Target/Mips/MipsISelLowering.cpp
View File

@@ -222,8 +222,10 @@ MipsTargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
}
if (!Subtarget->hasBitCount())
if (!Subtarget->hasBitCount()) {
setOperationAction(ISD::CTLZ, MVT::i32, Expand);
setOperationAction(ISD::CTLZ, MVT::i64, Expand);
}
if (!Subtarget->hasSwap()) {
setOperationAction(ISD::BSWAP, MVT::i32, Expand);

19
test/CodeGen/Mips/mips64countleading.ll Normal file
View File

@@ -0,0 +1,19 @@
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
define i64 @t1(i64 %X) nounwind readnone {
entry:
; CHECK: dclz
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
ret i64 %tmp1
}
declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
define i64 @t3(i64 %X) nounwind readnone {
entry:
; CHECK: dclo
%neg = xor i64 %X, -1
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
ret i64 %tmp1
}