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R600/SI: Use source modifier for f64 fabs

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215747 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
2014-08-15 18:42:15 +00:00
parent b5cb5e29a7
commit c882fc78fe
3 changed files with 127 additions and 2 deletions
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30
lib/Target/R600/SIISelLowering.cpp
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@@ -226,7 +226,6 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
// FIXME: These should be removed and handled the same was as f32 fneg. Source
// modifiers also work for the double instructions.
setOperationAction(ISD::FNEG, MVT::f64, Expand);
setOperationAction(ISD::FABS, MVT::f64, Expand);
setOperationAction(ISD::FDIV, MVT::f32, Custom);
@@ -665,6 +664,35 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MI->eraseFromParent();
break;
}
case AMDGPU::FABS64_SI: {
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
getTargetMachine().getSubtargetImpl()->getInstrInfo());
DebugLoc DL = MI->getDebugLoc();
unsigned SuperReg = MI->getOperand(0).getReg();
unsigned SrcReg = MI->getOperand(1).getReg();
unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
// Copy the subregister to make sure it is the right register class.
unsigned VReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
BuildMI(*BB, I, DL, TII->get(AMDGPU::COPY), VReg)
.addReg(SrcReg, 0, AMDGPU::sub1);
// We only need to mask the upper half of the register pair.
BuildMI(*BB, I, DL, TII->get(AMDGPU::V_AND_B32_e32), TmpReg)
.addImm(0x7fffffff)
.addReg(VReg);
BuildMI(*BB, I, DL, TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
.addReg(SrcReg, 0, AMDGPU::sub0)
.addImm(AMDGPU::sub0)
.addReg(TmpReg)
.addImm(AMDGPU::sub1);
MI->eraseFromParent();
break;
}
case AMDGPU::FNEG_SI: {
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(