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ARM MCRR/MCRR2 immediate operand range checking.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135192 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-07-14 21:26:42 +00:00
parent f546453466
commit c8ae39e746
5 changed files with 17 additions and 8 deletions
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4
lib/Target/ARM/ARMInstrInfo.td
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@@ -3701,7 +3701,7 @@ def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
class MovRRCopro<string opc, bit direction, class MovRRCopro<string opc, bit direction,
list<dag> pattern = [/* For disassembly only */]> list<dag> pattern = [/* For disassembly only */]>
: ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1, : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
GPR:$Rt, GPR:$Rt2, c_imm:$CRm), GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> { NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
let Inst{23-21} = 0b010; let Inst{23-21} = 0b010;
@@ -3727,7 +3727,7 @@ def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
class MovRRCopro2<string opc, bit direction, class MovRRCopro2<string opc, bit direction,
list<dag> pattern = [/* For disassembly only */]> list<dag> pattern = [/* For disassembly only */]>
: ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1, : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
!strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> { !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
let Inst{31-28} = 0b1111; let Inst{31-28} = 0b1111;

2
lib/Target/ARM/ARMInstrThumb2.td
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@@ -3355,7 +3355,7 @@ class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
class t2MovRRCopro<bits<4> Op, string opc, bit direction, class t2MovRRCopro<bits<4> Op, string opc, bit direction,
list<dag> pattern = []> list<dag> pattern = []>
: T2Cop<Op, (outs), : T2Cop<Op, (outs),
(ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
!strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> { !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
let Inst{27-24} = 0b1100; let Inst{27-24} = 0b1100;
let Inst{23-21} = 0b010; let Inst{23-21} = 0b010;

4
test/MC/ARM/arm_instructions.s
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@@ -91,15 +91,11 @@
@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee] @ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee]
mrc p14, #0, r1, c1, c2, #4 mrc p14, #0, r1, c1, c2, #4
@ CHECK: mcrr p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x44,0xec]
mcrr p7, #1, r5, r4, c1
@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xec] @ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xec]
mrrc p7, #1, r5, r4, c1 mrrc p7, #1, r5, r4, c1
@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe] @ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe]
mrc2 p14, #0, r1, c1, c2, #4 mrc2 p14, #0, r1, c1, c2, #4
@ CHECK: mcrr2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x44,0xfc]
mcrr2 p7, #1, r5, r4, c1
@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xfc] @ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xfc]
mrrc2 p7, #1, r5, r4, c1 mrrc2 p7, #1, r5, r4, c1

9
test/MC/ARM/basic-arm-instructions.s
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@@ -638,6 +638,15 @@ _func:
@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xee] @ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xee]
@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xfe] @ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xfe]
@------------------------------------------------------------------------------
@ MCRR/MCRR2
@------------------------------------------------------------------------------
mcrr p7, #15, r5, r4, c1
mcrr2 p7, #15, r5, r4, c1
@ CHECK: mcrr p7, #15, r5, r4, c1 @ encoding: [0xf1,0x57,0x44,0xec]
@ CHECK: mcrr2 p7, #15, r5, r4, c1 @ encoding: [0xf1,0x57,0x44,0xfc]
@------------------------------------------------------------------------------ @------------------------------------------------------------------------------
@ STM* @ STM*
@------------------------------------------------------------------------------ @------------------------------------------------------------------------------

6
test/MC/ARM/diagnostics.s
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@@ -69,11 +69,15 @@
@ Double-check that we're synced up with the right diagnostics. @ Double-check that we're synced up with the right diagnostics.
@ CHECK-ERRORS: dbg #16 @ CHECK-ERRORS: dbg #16
@ Out of range immediate for MCR/MCR2 @ Out of range immediate for MCR/MCR2/MCRR/MCRR2
mcr p7, #8, r5, c1, c1, #4 mcr p7, #8, r5, c1, c1, #4
mcr p7, #2, r5, c1, c1, #8 mcr p7, #2, r5, c1, c1, #8
mcr2 p7, #8, r5, c1, c1, #4 mcr2 p7, #8, r5, c1, c1, #4
mcr2 p7, #1, r5, c1, c1, #8 mcr2 p7, #1, r5, c1, c1, #8
mcrr p7, #16, r5, r4, c1
mcrr2 p7, #16, r5, r4, c1
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction