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Add missing zmovl AVX patterns which were causing crashes.
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146689 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -618,6 +618,9 @@ let Predicates = [HasAVX] in {
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(SUBREG_TO_REG (i64 0),
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(v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
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sub_xmm)>;
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def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
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(v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
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(SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
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// Move low f64 and clear high bits.
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def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
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@ -800,6 +803,9 @@ let Predicates = [HasAVX] in {
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def : Pat<(v8i32 (X86vzmovl
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(insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
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(SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
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def : Pat<(v4i64 (X86vzmovl
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(insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
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(SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
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def : Pat<(v8f32 (X86vzmovl
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(insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
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(SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
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@ -61,3 +61,11 @@ t2.exit: ; preds = %0, %loop
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return: ; preds = %loop.cond
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ret void
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}
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define <3 x i64> @t4() nounwind {
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entry:
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%0 = load <2 x i64> addrspace(1)* undef, align 16
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%1 = extractelement <2 x i64> %0, i32 0
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%2 = insertelement <3 x i64> <i64 undef, i64 0, i64 0>, i64 %1, i32 0
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ret <3 x i64> %2
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}
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