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[Hexagon] Adding V4 logic-logic instructions and tests.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225198 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2015-01-05 20:14:58 +00:00
parent e48ec2a918
commit c8e734a561
2 changed files with 81 additions and 0 deletions
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55
lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -1819,6 +1819,61 @@ def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd),
let Inst{4-0} = Rd;
}
let isCodeGenOnly = 0 in {
// Rx[&|]=xor(Rs,Rt)
def M4_or_xor : T_MType_acc_rr < "|= xor", 0b110, 0b001, 0>;
def M4_and_xor : T_MType_acc_rr < "&= xor", 0b010, 0b010, 0>;
// Rx[&|^]=or(Rs,Rt)
def M4_xor_or : T_MType_acc_rr < "^= or", 0b110, 0b011, 0>;
let CextOpcode = "ORr_ORr" in
def M4_or_or : T_MType_acc_rr < "|= or", 0b110, 0b000, 0>;
def M4_and_or : T_MType_acc_rr < "&= or", 0b010, 0b001, 0>;
// Rx[&|^]=and(Rs,Rt)
def M4_xor_and : T_MType_acc_rr < "^= and", 0b110, 0b010, 0>;
let CextOpcode = "ORr_ANDr" in
def M4_or_and : T_MType_acc_rr < "|= and", 0b010, 0b011, 0>;
def M4_and_and : T_MType_acc_rr < "&= and", 0b010, 0b000, 0>;
// Rx[&|^]=and(Rs,~Rt)
def M4_xor_andn : T_MType_acc_rr < "^= and", 0b001, 0b010, 0, [], 1>;
def M4_or_andn : T_MType_acc_rr < "|= and", 0b001, 0b000, 0, [], 1>;
def M4_and_andn : T_MType_acc_rr < "&= and", 0b001, 0b001, 0, [], 1>;
}
// Compound or-or and or-and
let isExtentSigned = 1, InputType = "imm", hasNewValue = 1, isExtendable = 1,
opExtentBits = 10, opExtendable = 3 in
class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode>
: MInst_acc <(outs IntRegs:$Rx),
(ins IntRegs:$src1, IntRegs:$Rs, s10Ext:$s10),
"$Rx |= "#mnemonic#"($Rs, #$s10)",
[(set (i32 IntRegs:$Rx), (or (i32 IntRegs:$src1),
(OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10)))],
"$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel {
bits<5> Rx;
bits<5> Rs;
bits<10> s10;
let IClass = 0b1101;
let Inst{27-24} = 0b1010;
let Inst{23-22} = MajOp;
let Inst{20-16} = Rs;
let Inst{21} = s10{9};
let Inst{13-5} = s10{8-0};
let Inst{4-0} = Rx;
}
let CextOpcode = "ORr_ANDr", isCodeGenOnly = 0 in
def S4_or_andi : T_CompOR <"and", 0b00, and>;
let CextOpcode = "ORr_ORr", isCodeGenOnly = 0 in
def S4_or_ori : T_CompOR <"or", 0b10, or>;
// Add and accumulate.
// Rd=add(Rs,add(Ru,#s6))
let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 6,

26
test/MC/Disassembler/Hexagon/xtype_alu.txt
View File

@ -64,10 +64,36 @@
# CHECK: r17:16 = or(r21:20, ~r31:30)
0x10 0xde 0x94 0xca
# CHECK: r17:16 ^= xor(r21:20, r31:30)
0xf1 0xc3 0x15 0xda
# CHECK: r17 |= and(r21, #31)
0xf5 0xc3 0x51 0xda
# CHECK: r17 = or(r21, and(r17, #31))
0xf1 0xc3 0x95 0xda
# CHECK: r17 |= or(r21, #31)
0x11 0xdf 0x35 0xef
# CHECK: r17 |= and(r21, ~r31)
0x31 0xdf 0x35 0xef
# CHECK: r17 &= and(r21, ~r31)
0x51 0xdf 0x35 0xef
# CHECK: r17 ^= and(r21, ~r31)
0x11 0xdf 0x55 0xef
# CHECK: r17 &= and(r21, r31)
0x31 0xdf 0x55 0xef
# CHECK: r17 &= or(r21, r31)
0x51 0xdf 0x55 0xef
# CHECK: r17 &= xor(r21, r31)
0x71 0xdf 0x55 0xef
# CHECK: r17 |= and(r21, r31)
0x71 0xdf 0x95 0xef
# CHECK: r17 ^= xor(r21, r31)
0x11 0xdf 0xd5 0xef
# CHECK: r17 |= or(r21, r31)
0x31 0xdf 0xd5 0xef
# CHECK: r17 |= xor(r21, r31)
0x51 0xdf 0xd5 0xef
# CHECK: r17 ^= and(r21, r31)
0x71 0xdf 0xd5 0xef
# CHECK: r17 ^= or(r21, r31)
0x11 0xdf 0xd5 0xd5
# CHECK: r17 = max(r21, r31)
0x91 0xdf 0xd5 0xd5