mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-06 06:33:24 +00:00
Unbreak build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117155 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
364f17c471
commit
c8f46c45a0
@ -1253,6 +1253,17 @@ bool MachineInstr::allDefsAreDead() const {
|
||||
return true;
|
||||
}
|
||||
|
||||
/// copyImplicitOps - Copy implicit register operands from specified
|
||||
/// instruction to this instruction.
|
||||
void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
|
||||
for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
|
||||
i != e; ++i) {
|
||||
const MachineOperand &MO = MI->getOperand(i);
|
||||
if (MO.isReg() && MO.isImplicit())
|
||||
addOperand(MO);
|
||||
}
|
||||
}
|
||||
|
||||
void MachineInstr::dump() const {
|
||||
dbgs() << " " << *this;
|
||||
}
|
||||
|
@ -285,16 +285,6 @@ bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
|
||||
return false;
|
||||
}
|
||||
|
||||
static void
|
||||
TransferImplicitOps(MachineInstr *MI, MachineInstr *NewMI) {
|
||||
for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
|
||||
i != e; ++i) {
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (MO.isReg() && MO.isImplicit())
|
||||
NewMI->addOperand(MO);
|
||||
}
|
||||
}
|
||||
|
||||
/// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with
|
||||
/// IntA being the source and IntB being the dest, thus this defines a value
|
||||
/// number in IntB. If the source value number (in IntA) is defined by a
|
||||
|
Loading…
x
Reference in New Issue
Block a user