mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-01 00:33:09 +00:00
Spelling!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159936 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
2b6652fb10
commit
c985e6ece6
@ -7294,7 +7294,7 @@ processInstruction(MCInst &Inst,
|
||||
case ARM::t2RORrr:
|
||||
case ARM::t2BICrr:
|
||||
{
|
||||
// Assemblers should use the narrow encodings of these instructions when permissable.
|
||||
// Assemblers should use the narrow encodings of these instructions when permissible.
|
||||
if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
|
||||
isARMLowRegister(Inst.getOperand(2).getReg())) &&
|
||||
Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
|
||||
@ -7330,7 +7330,7 @@ processInstruction(MCInst &Inst,
|
||||
case ARM::t2ADCrr:
|
||||
case ARM::t2ORRrr:
|
||||
{
|
||||
// Assemblers should use the narrow encodings of these instructions when permissable.
|
||||
// Assemblers should use the narrow encodings of these instructions when permissible.
|
||||
// These instructions are special in that they are commutable, so shorter encodings
|
||||
// are available more often.
|
||||
if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
|
||||
|
Loading…
Reference in New Issue
Block a user