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MIR Serialization: Serialize simple MachineRegisterInfo attributes.

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This commit serializes the 3 scalar boolean attributes from the
MachineRegisterInfo class: IsSSA, TracksRegLiveness, and
TracksSubRegLiveness. These attributes are serialized as part
of the machine function YAML mapping.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10618


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240579 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alex Lorenz
2015-06-24 19:56:10 +00:00
parent fa21ae52f0
commit c9a4f3d5d9
5 changed files with 79 additions and 4 deletions
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10
include/llvm/CodeGen/MIRYamlMapping.h
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@@ -97,6 +97,13 @@ struct MachineFunction {
unsigned Alignment = 0;
bool ExposesReturnsTwice = false;
bool HasInlineAsm = false;
// Register information
bool IsSSA = false;
bool TracksRegLiveness = false;
bool TracksSubRegLiveness = false;
// TODO: Serialize virtual register definitions.
// TODO: Serialize the various register masks.
// TODO: Serialize live in registers.
std::vector<MachineBasicBlock> BasicBlocks;
};
@@ -107,6 +114,9 @@ template <> struct MappingTraits<MachineFunction> {
YamlIO.mapOptional("alignment", MF.Alignment);
YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice);
YamlIO.mapOptional("hasInlineAsm", MF.HasInlineAsm);
YamlIO.mapOptional("isSSA", MF.IsSSA);
YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
YamlIO.mapOptional("body", MF.BasicBlocks);
}
};