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https://github.com/c64scene-ar/llvm-6502.git
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[FastISel][AArch64] Add vector support to argument lowering.
Lower the first 8 vector arguments too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217850 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
parent
bad2c13aae
commit
c9bc145e31
@ -2096,8 +2096,7 @@ bool AArch64FastISel::fastLowerArguments() {
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if (CC != CallingConv::C)
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return false;
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// Only handle simple cases like i1/i8/i16/i32/i64/f32/f64 of up to 8 GPR and
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// FPR each.
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// Only handle simple cases of up to 8 GPR and FPR each.
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unsigned GPRCnt = 0;
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unsigned FPRCnt = 0;
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unsigned Idx = 0;
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@ -2111,32 +2110,34 @@ bool AArch64FastISel::fastLowerArguments() {
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return false;
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Type *ArgTy = Arg.getType();
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if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
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if (ArgTy->isStructTy() || ArgTy->isArrayTy())
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return false;
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EVT ArgVT = TLI.getValueType(ArgTy);
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if (!ArgVT.isSimple()) return false;
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switch (ArgVT.getSimpleVT().SimpleTy) {
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default: return false;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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if (!ArgVT.isSimple())
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return false;
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MVT VT = ArgVT.getSimpleVT().SimpleTy;
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if (VT.isFloatingPoint() && !Subtarget->hasFPARMv8())
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return false;
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if (VT.isVector() &&
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(!Subtarget->hasNEON() || !Subtarget->isLittleEndian()))
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return false;
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if (VT >= MVT::i1 && VT <= MVT::i64)
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++GPRCnt;
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break;
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case MVT::f16:
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case MVT::f32:
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case MVT::f64:
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else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() ||
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VT.is128BitVector())
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++FPRCnt;
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break;
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}
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else
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return false;
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if (GPRCnt > 8 || FPRCnt > 8)
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return false;
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}
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static const MCPhysReg Registers[5][8] = {
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static const MCPhysReg Registers[6][8] = {
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{ AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
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AArch64::W5, AArch64::W6, AArch64::W7 },
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{ AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
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@ -2146,7 +2147,9 @@ bool AArch64FastISel::fastLowerArguments() {
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{ AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
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AArch64::S5, AArch64::S6, AArch64::S7 },
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{ AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
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AArch64::D5, AArch64::D6, AArch64::D7 }
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AArch64::D5, AArch64::D6, AArch64::D7 },
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{ AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
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AArch64::Q5, AArch64::Q6, AArch64::Q7 }
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};
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unsigned GPRIdx = 0;
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@ -2154,29 +2157,28 @@ bool AArch64FastISel::fastLowerArguments() {
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for (auto const &Arg : F->args()) {
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MVT VT = TLI.getSimpleValueType(Arg.getType());
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unsigned SrcReg;
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const TargetRegisterClass *RC = nullptr;
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switch (VT.SimpleTy) {
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default: llvm_unreachable("Unexpected value type.");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16: VT = MVT::i32; // fall-through
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case MVT::i32:
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SrcReg = Registers[0][GPRIdx++]; RC = &AArch64::GPR32RegClass; break;
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case MVT::i64:
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SrcReg = Registers[1][GPRIdx++]; RC = &AArch64::GPR64RegClass; break;
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case MVT::f16:
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SrcReg = Registers[2][FPRIdx++]; RC = &AArch64::FPR16RegClass; break;
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case MVT::f32:
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SrcReg = Registers[3][FPRIdx++]; RC = &AArch64::FPR32RegClass; break;
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case MVT::f64:
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SrcReg = Registers[4][FPRIdx++]; RC = &AArch64::FPR64RegClass; break;
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}
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// Skip unused arguments.
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if (Arg.use_empty()) {
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updateValueMap(&Arg, 0);
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continue;
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}
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const TargetRegisterClass *RC;
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if (VT >= MVT::i1 && VT <= MVT::i32) {
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SrcReg = Registers[0][GPRIdx++];
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RC = &AArch64::GPR32RegClass;
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VT = MVT::i32;
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} else if (VT == MVT::i64) {
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SrcReg = Registers[1][GPRIdx++];
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RC = &AArch64::GPR64RegClass;
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} else if (VT == MVT::f16) {
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SrcReg = Registers[2][FPRIdx++];
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RC = &AArch64::FPR16RegClass;
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} else if (VT == MVT::f32) {
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SrcReg = Registers[3][FPRIdx++];
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RC = &AArch64::FPR32RegClass;
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} else if ((VT == MVT::f64) || VT.is64BitVector()) {
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SrcReg = Registers[4][FPRIdx++];
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RC = &AArch64::FPR64RegClass;
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} else if (VT.is128BitVector()) {
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SrcReg = Registers[5][FPRIdx++];
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RC = &AArch64::FPR128RegClass;
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} else
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llvm_unreachable("Unexpected value type.");
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unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
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// FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
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74
test/CodeGen/AArch64/fast-isel-vector-arithmetic.ll
Normal file
74
test/CodeGen/AArch64/fast-isel-vector-arithmetic.ll
Normal file
@ -0,0 +1,74 @@
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; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -fast-isel-abort-args -verify-machineinstrs < %s | FileCheck %s
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; Vector Integer Add
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define <8 x i8> @add_v8i8_rr(<8 x i8> %a, <8 x i8> %b) {
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; CHECK: add_v8i8_rr
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; CHECK: add.8b v0, v0, v1
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%1 = add <8 x i8> %a, %b
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ret <8 x i8> %1
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}
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define <16 x i8> @add_v16i8_rr(<16 x i8> %a, <16 x i8> %b) {
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; CHECK: add_v16i8_rr
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; CHECK: add.16b v0, v0, v1
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%1 = add <16 x i8> %a, %b
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ret <16 x i8> %1
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}
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define <4 x i16> @add_v4i16_rr(<4 x i16> %a, <4 x i16> %b) {
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; CHECK: add_v4i16_rr
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; CHECK: add.4h v0, v0, v1
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%1 = add <4 x i16> %a, %b
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ret <4 x i16> %1
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}
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define <8 x i16> @add_v8i16_rr(<8 x i16> %a, <8 x i16> %b) {
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; CHECK: add_v8i16_rr
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; CHECK: add.8h v0, v0, v1
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%1 = add <8 x i16> %a, %b
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ret <8 x i16> %1
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}
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define <2 x i32> @add_v2i32_rr(<2 x i32> %a, <2 x i32> %b) {
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; CHECK: add_v2i32_rr
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; CHECK: add.2s v0, v0, v1
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%1 = add <2 x i32> %a, %b
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ret <2 x i32> %1
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}
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define <4 x i32> @add_v4i32_rr(<4 x i32> %a, <4 x i32> %b) {
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; CHECK: add_v4i32_rr
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; CHECK: add.4s v0, v0, v1
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%1 = add <4 x i32> %a, %b
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ret <4 x i32> %1
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}
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define <2 x i64> @add_v2i64_rr(<2 x i64> %a, <2 x i64> %b) {
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; CHECK: add_v2i64_rr
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; CHECK: add.2d v0, v0, v1
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%1 = add <2 x i64> %a, %b
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ret <2 x i64> %1
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}
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; Vector Floating-point Add
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define <2 x float> @add_v2f32_rr(<2 x float> %a, <2 x float> %b) {
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; CHECK: add_v2f32_rr
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; CHECK: fadd.2s v0, v0, v1
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%1 = fadd <2 x float> %a, %b
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ret <2 x float> %1
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}
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define <4 x float> @add_v4f32_rr(<4 x float> %a, <4 x float> %b) {
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; CHECK: add_v4f32_rr
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; CHECK: fadd.4s v0, v0, v1
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%1 = fadd <4 x float> %a, %b
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ret <4 x float> %1
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}
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define <2 x double> @add_v2f64_rr(<2 x double> %a, <2 x double> %b) {
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; CHECK: add_v2f64_rr
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; CHECK: fadd.2d v0, v0, v1
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%1 = fadd <2 x double> %a, %b
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ret <2 x double> %1
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}
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