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Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146630 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1792,7 +1792,8 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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case ISD::BITCAST:
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// If this is an FP->Int bitcast and if the sign bit is the only
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// thing demanded, turn this into a FGETSIGN.
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if (!Op.getValueType().isVector() &&
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if (!TLO.LegalOperations() &&
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!Op.getValueType().isVector() &&
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!Op.getOperand(0).getValueType().isVector() &&
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NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
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Op.getOperand(0).getValueType().isFloatingPoint()) {
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@ -78,6 +78,22 @@ entry:
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ret i32 %shr.i
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}
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; PR11570
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define void @float_call_signbit(double %n) {
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entry:
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; FIXME: This should also use movmskps; we don't form the FGETSIGN node
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; in this case, though.
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; CHECK: float_call_signbit:
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; CHECK: movd %xmm0, %rdi
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; FIXME
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%t0 = bitcast double %n to i64
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%tobool.i.i.i.i = icmp slt i64 %t0, 0
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tail call void @float_call_signbit_callee(i1 zeroext %tobool.i.i.i.i)
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ret void
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}
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declare void @float_call_signbit_callee(i1 zeroext)
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; rdar://10247336
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; movmskp{s|d} only set low 4/2 bits, high bits are known zero
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