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IR: add a second ordering operand to cmpxhg for failure
The syntax for "cmpxchg" should now look something like: cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic where the second ordering argument gives the required semantics in the case that no exchange takes place. It should be no stronger than the first ordering constraint and cannot be either "release" or "acq_rel" (since no store will have taken place). rdar://problem/15996804 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203559 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1441,9 +1441,11 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
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pushValue(I.getOperand(2), InstID, Vals, VE); // newval.
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Vals.push_back(cast<AtomicCmpXchgInst>(I).isVolatile());
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Vals.push_back(GetEncodedOrdering(
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cast<AtomicCmpXchgInst>(I).getOrdering()));
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cast<AtomicCmpXchgInst>(I).getSuccessOrdering()));
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Vals.push_back(GetEncodedSynchScope(
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cast<AtomicCmpXchgInst>(I).getSynchScope()));
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Vals.push_back(GetEncodedOrdering(
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cast<AtomicCmpXchgInst>(I).getFailureOrdering()));
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break;
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case Instruction::AtomicRMW:
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Code = bitc::FUNC_CODE_INST_ATOMICRMW;
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