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FP 0.0 setcc optimization, and generate short branch sequence for setcc(FP) rather than stack usage

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20589 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2005-03-14 19:23:45 +00:00
parent b2b17bb65b
commit ca3d59b1dc
2 changed files with 37 additions and 19 deletions
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48
lib/Target/Alpha/AlphaISelPattern.cpp
View File

@ -1253,8 +1253,20 @@ unsigned ISel::SelectExpr(SDOperand N) {
case ISD::SETNE: Opc = Alpha::CMPTEQ; inv = true; break; case ISD::SETNE: Opc = Alpha::CMPTEQ; inv = true; break;
} }
Tmp1 = SelectExpr(N.getOperand(0)); //FIXME: check for constant 0.0
Tmp2 = SelectExpr(N.getOperand(1)); ConstantFPSDNode *CN;
if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(0)))
&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
Tmp1 = Alpha::F31;
else
Tmp1 = SelectExpr(N.getOperand(0));
if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1)))
&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
Tmp2 = Alpha::F31;
else
Tmp2 = SelectExpr(N.getOperand(1));
//Can only compare doubles, and dag won't promote for me //Can only compare doubles, and dag won't promote for me
if (SetCC->getOperand(0).getValueType() == MVT::f32) if (SetCC->getOperand(0).getValueType() == MVT::f32)
{ {
@ -1280,22 +1292,24 @@ unsigned ISel::SelectExpr(SDOperand N) {
//now arrange for Result (int) to have a 1 or 0 //now arrange for Result (int) to have a 1 or 0
// Spill the FP to memory and reload it from there. BuildMI(BB, Alpha::CC2INT, 1, Result).addReg(Tmp3);
unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
MachineFunction *F = BB->getParent(); // // Spill the FP to memory and reload it from there.
int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8); // unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
unsigned Tmp4 = MakeReg(MVT::f64); // MachineFunction *F = BB->getParent();
BuildMI(BB, Alpha::CVTTQ, 1, Tmp4).addReg(Tmp3); // int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8);
BuildMI(BB, Alpha::STT, 3).addReg(Tmp4).addFrameIndex(FrameIdx).addReg(Alpha::F31); // unsigned Tmp4 = MakeReg(MVT::f64);
unsigned Tmp5 = MakeReg(MVT::i64); // BuildMI(BB, Alpha::CVTTQ, 1, Tmp4).addReg(Tmp3);
BuildMI(BB, Alpha::LDQ, 2, Tmp5).addFrameIndex(FrameIdx).addReg(Alpha::F31); // BuildMI(BB, Alpha::STT, 3).addReg(Tmp4).addFrameIndex(FrameIdx).addReg(Alpha::F31);
// unsigned Tmp5 = MakeReg(MVT::i64);
// BuildMI(BB, Alpha::LDQ, 2, Tmp5).addFrameIndex(FrameIdx).addReg(Alpha::F31);
//now, set result based on Tmp5 // //now, set result based on Tmp5
//Set Tmp6 if fp cmp was false // //Set Tmp6 if fp cmp was false
unsigned Tmp6 = MakeReg(MVT::i64); // unsigned Tmp6 = MakeReg(MVT::i64);
BuildMI(BB, Alpha::CMPEQ, 2, Tmp6).addReg(Tmp5).addReg(Alpha::R31); // BuildMI(BB, Alpha::CMPEQ, 2, Tmp6).addReg(Tmp5).addReg(Alpha::R31);
//and invert // //and invert
BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Tmp6).addReg(Alpha::R31); // BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Tmp6).addReg(Alpha::R31);
} }
// else // else

8
lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -43,11 +43,11 @@ let Defs = [R29] in
let isCall = 1, let isCall = 1,
Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
R20, R21, R22, R23, R24, R25, R26, R27, R29, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
F0, F1, F0, F1,
F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30],
Uses = [R27, R29] in Uses = [R29] in
def CALL : PseudoInstAlpha< (ops s64imm:$TARGET), "jsr $TARGET">; //Jump to subroutine def CALL : PseudoInstAlpha< (ops s64imm:$TARGET), "jsr $TARGET">; //Jump to subroutine
let isReturn = 1, isTerminator = 1 in let isReturn = 1, isTerminator = 1 in
@ -87,6 +87,10 @@ let Uses = [R29],
def DIVQ : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "divq $RA,$RB,$$27">; //signed division def DIVQ : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "divq $RA,$RB,$$27">; //signed division
} }
//This is an improvement on the old style setcc (FP)
def CC2INT : PseudoInstAlpha<(ops GPRC:$RES, FPRC:$COND),
"lda $RES,1($$31)\n\tfbeq $COND, 42f\n\tbis $$31,$$31,$RES\n42:\n">;
//*********************** //***********************
//Real instructions //Real instructions
//*********************** //***********************