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Add support for the vector-widening of vselect and vector-setcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142488 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -633,6 +633,7 @@ private:
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SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
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SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N);
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SDValue WidenVecOp_STORE(SDNode* N);
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SDValue WidenVecOp_SETCC(SDNode* N, unsigned ResNo);
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SDValue WidenVecOp_Convert(SDNode *N);
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@ -1239,6 +1239,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
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case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
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case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
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case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
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case ISD::VSELECT:
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case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
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case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
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case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
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@ -1928,7 +1929,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
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SDValue InOp1 = GetWidenedVector(N->getOperand(1));
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SDValue InOp2 = GetWidenedVector(N->getOperand(2));
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assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
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return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
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return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
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WidenVT, Cond1, InOp1, InOp2);
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}
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@ -2032,6 +2033,7 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
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case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
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case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
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case ISD::STORE: Res = WidenVecOp_STORE(N); break;
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case ISD::SETCC: Res = WidenVecOp_SETCC(N, ResNo); break;
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case ISD::FP_EXTEND:
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case ISD::FP_TO_SINT:
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@ -2165,6 +2167,30 @@ SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
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MVT::Other,&StChain[0],StChain.size());
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}
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SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N, unsigned ResNo) {
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assert(ResNo < 2 && "Invalid res num to widen");
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SDValue InOp0 = GetWidenedVector(N->getOperand(0));
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SDValue InOp1 = GetWidenedVector(N->getOperand(1));
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EVT VT = InOp0.getValueType();
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DebugLoc dl = N->getDebugLoc();
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// WARNING: In this code we widen the compare instruction with garbage.
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// This garbage may contain denormal floats which may be slow. Is this a real
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// concern ? Should we zero the unused lanes if this is a float compare ?
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SDValue Zero = DAG.getIntPtrConstant(0);
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EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
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N->getValueType(0).getVectorElementType(),
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VT.getVectorNumElements());
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SDValue WideSETCC = DAG.getNode(ISD::SETCC, N->getDebugLoc(),
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ResVT, InOp0, InOp1, N->getOperand(2));
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return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, N->getValueType(0),
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WideSETCC, Zero);
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}
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//===----------------------------------------------------------------------===//
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// Vector Widening Utilities
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//===----------------------------------------------------------------------===//
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68
test/CodeGen/X86/2011-10-19-widen_vselect.ll
Normal file
68
test/CodeGen/X86/2011-10-19-widen_vselect.ll
Normal file
@ -0,0 +1,68 @@
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; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s
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target triple = "x86_64-unknown-linux-gnu"
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; Make sure that we don't crash when legalizng vselect and vsetcc and that
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; we are able to generate vector blend instructions.
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; CHECK: simple_widen
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; CHECK: blend
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; CHECK: ret
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define void @simple_widen() {
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entry:
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%0 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef
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store <2 x float> %0, <2 x float>* undef
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ret void
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}
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; CHECK: complex_inreg_work
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; CHECK: blend
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; CHECK: ret
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define void @complex_inreg_work() {
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entry:
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%0 = fcmp oeq <2 x float> undef, undef
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%1 = select <2 x i1> %0, <2 x float> undef, <2 x float> undef
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store <2 x float> %1, <2 x float>* undef
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ret void
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}
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; CHECK: zero_test
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; CHECK: blend
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; CHECK: ret
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define void @zero_test() {
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entry:
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%0 = select <2 x i1> undef, <2 x float> undef, <2 x float> zeroinitializer
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store <2 x float> %0, <2 x float>* undef
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ret void
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}
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; CHECK: full_test
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; CHECK: blend
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; CHECK: ret
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define void @full_test() {
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entry:
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%Cy300 = alloca <4 x float>
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%Cy11a = alloca <2 x float>
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%Cy118 = alloca <2 x float>
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%Cy119 = alloca <2 x float>
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br label %B1
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B1: ; preds = %entry
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%0 = load <2 x float>* %Cy119
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%1 = fptosi <2 x float> %0 to <2 x i32>
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%2 = sitofp <2 x i32> %1 to <2 x float>
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%3 = fcmp ogt <2 x float> %0, zeroinitializer
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%4 = fadd <2 x float> %2, <float 1.000000e+00, float 1.000000e+00>
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%5 = select <2 x i1> %3, <2 x float> %4, <2 x float> %2
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%6 = fcmp oeq <2 x float> %2, %0
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%7 = select <2 x i1> %6, <2 x float> %0, <2 x float> %5
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store <2 x float> %7, <2 x float>* %Cy118
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%8 = load <2 x float>* %Cy118
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store <2 x float> %8, <2 x float>* %Cy11a
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ret void
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}
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