6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-07 14:33:15 +00:00
Code Issues Projects Releases Wiki Activity

Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do

Browse Source 
64-bit vector shuffle.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26964 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-03-22 22:07:06 +00:00
parent 7de48c143a
commit ca6e8eafd2
3 changed files with 7 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
include/llvm/Target/TargetLowering.h
View File

@ -202,7 +202,7 @@ public:
/// support and the code generator is tasked with not creating illegal masks. /// support and the code generator is tasked with not creating illegal masks.
bool isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const { bool isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const {
return isOperationLegal(ISD::VECTOR_SHUFFLE, VT) && return isOperationLegal(ISD::VECTOR_SHUFFLE, VT) &&
isShuffleMaskLegal(Mask); isShuffleMaskLegal(Mask, VT);
} }
/// getTypeToPromoteTo - If the action for this operation is to promote, this /// getTypeToPromoteTo - If the action for this operation is to promote, this
@ -489,7 +489,7 @@ protected:
/// support *some* VECTOR_SHUFFLE operations, those with specific masks. /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
/// are assumed to be legal. /// are assumed to be legal.
virtual bool isShuffleMaskLegal(SDOperand Mask) const { virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
return true; return true;
} }

5
lib/Target/X86/X86ISelLowering.cpp
View File

@ -2371,7 +2371,10 @@ bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
/// support *some* VECTOR_SHUFFLE operations, those with specific masks. /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
/// are assumed to be legal. /// are assumed to be legal.
bool X86TargetLowering::isShuffleMaskLegal(SDOperand Mask) const { bool
X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
// Only do shuffles on 128-bit vector types for now.
if (MVT::getSizeInBits(VT) == 64) return false;
return (X86::isSplatMask(Mask.Val) || return (X86::isSplatMask(Mask.Val) ||
(Subtarget->hasSSE2() && X86::isPSHUFDMask(Mask.Val))); (Subtarget->hasSSE2() && X86::isPSHUFDMask(Mask.Val)));
} }

2
lib/Target/X86/X86ISelLowering.h
View File

@ -267,7 +267,7 @@ namespace llvm {
/// support *some* VECTOR_SHUFFLE operations, those with specific masks. /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
/// are assumed to be legal. /// are assumed to be legal.
virtual bool isShuffleMaskLegal(SDOperand Mask) const; virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
private: private:
// C Calling Convention implementation. // C Calling Convention implementation.
std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG); std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG);