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The single check for N64 inside MipsDisassemblerBase's subclasses is actually wrong. It should be testing for FeatureGP64bit.There are no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224339 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -36,15 +36,15 @@ public:
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MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
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MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
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bool IsBigEndian)
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bool IsBigEndian)
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: MCDisassembler(STI, Ctx),
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: MCDisassembler(STI, Ctx),
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IsN64(STI.getFeatureBits() & Mips::FeatureN64),
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IsGP64Bit(STI.getFeatureBits() & Mips::FeatureGP64Bit),
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IsBigEndian(IsBigEndian) {}
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IsBigEndian(IsBigEndian) {}
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virtual ~MipsDisassemblerBase() {}
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virtual ~MipsDisassemblerBase() {}
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bool isN64() const { return IsN64; }
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bool isGP64Bit() const { return IsGP64Bit; }
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private:
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private:
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bool IsN64;
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bool IsGP64Bit;
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protected:
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protected:
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bool IsBigEndian;
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bool IsBigEndian;
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};
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};
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@ -974,7 +974,7 @@ static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
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unsigned RegNo,
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unsigned RegNo,
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uint64_t Address,
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uint64_t Address,
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const void *Decoder) {
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const void *Decoder) {
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if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
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if (static_cast<const MipsDisassembler *>(Decoder)->isGP64Bit())
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return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
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return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
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return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
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return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
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