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Do not use register as base ptr of pre- and post- inc/dec load / store nodes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71098 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-05-06 18:25:01 +00:00
parent ee08da8956
commit caab129cd1
2 changed files with 15 additions and 1 deletions
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5
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -4536,7 +4536,7 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
// Check #1. Preinc'ing a frame index would require copying the stack pointer
// (plus the implicit offset) to a register to preinc anyway.
if (isa<FrameIndexSDNode>(BasePtr))
if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
return false;
// Check #2.
@ -4663,6 +4663,9 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
// nor a successor of N. Otherwise, if Op is folded that would
// create a cycle.
if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
continue;
// Check for #1.
bool TryNext = false;
for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),

11
test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll Normal file
View File

@ -0,0 +1,11 @@
; RUN: llvm-as < %s | llc -mtriple=arm-linuxeabi-unknown-gnu -mattr=+v6
; PR4166
%"byte[]" = type { i32, i8* }
%tango.time.Time.Time = type { i64 }
define fastcc void @t() {
entry:
%tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval null) ; <i1> [#uses=0]
ret void
}