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Add missing mayLoad flags to a large class of AVX *_Int instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162622 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-08-24 23:29:07 +00:00
parent 36ff8f25c5
commit cac59d8ae8
1 changed files with 2 additions and 1 deletions
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3
lib/Target/X86/X86InstrSSE.td
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@ -2986,7 +2986,7 @@ multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2), def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>; "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
let mayLoad = 1 in let mayLoad = 1 in {
def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2), def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>; "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
@ -2994,6 +2994,7 @@ multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
(ins VR128:$src1, ssmem:$src2), (ins VR128:$src1, ssmem:$src2),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>; "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
}
} }
/// sse1_fp_unop_p - SSE1 unops in packed form. /// sse1_fp_unop_p - SSE1 unops in packed form.