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ARM: try to add extra CS-register whenever stack alignment >= 8.

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We currently try to push an even number of registers to preserve 8-byte
alignment during a function's prologue, but only when the stack alignment is
prcisely 8. Many of the reasons for doing it apply also when that alignment > 8
(the extra store is often free, and can save another stack adjustment, though
less frequently for 16-byte stack alignment).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221321 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-11-05 00:27:20 +00:00
parent 1f771b80c0
commit cafa378fe0
2 changed files with 3 additions and 3 deletions
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2
lib/Target/ARM/ARMFrameLowering.cpp
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@ -1575,7 +1575,7 @@ ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
// of GPRs, spill one extra callee save GPR so we won't have to pad between
// the integer and double callee save areas.
unsigned TargetAlign = getStackAlignment();
if (TargetAlign == 8 && (NumGPRSpills & 1)) {
if (TargetAlign >= 8 && (NumGPRSpills & 1)) {
if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
unsigned Reg = UnspilledCS1GPRs[i];

4
test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll
View File

@ -22,9 +22,9 @@ define void @varargs_func(i32 %arg1, ...) {
; Reserve space for the varargs save area. This currently reserves
; more than enough (16 bytes rather than the 12 bytes needed).
; CHECK: sub sp, sp, #16
; CHECK: push {lr}
; CHECK: push {r11, lr}
; Align the stack pointer to a multiple of 16.
; CHECK: sub sp, sp, #12
; CHECK: sub sp, sp, #8
; Calculate the address of the varargs save area and save varargs
; arguments into it.
; CHECK-NEXT: add r0, sp, #20