From cb50e0bd60167440e2e41274f9d3c3c0e88d90ad Mon Sep 17 00:00:00 2001 From: Anton Korobeynikov Date: Fri, 15 Jan 2010 21:18:18 +0000 Subject: [PATCH] Enable bit tests and setcc stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93552 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/MSP430/MSP430ISelLowering.cpp | 10 ++++--- lib/Target/MSP430/MSP430InstrInfo.td | 35 +++++++++++++----------- 2 files changed, 25 insertions(+), 20 deletions(-) diff --git a/lib/Target/MSP430/MSP430ISelLowering.cpp b/lib/Target/MSP430/MSP430ISelLowering.cpp index d1ce3cfe99c..aea8befde1e 100644 --- a/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -755,6 +755,8 @@ SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { // If we are doing an AND and testing against zero, then the CMP // will not be generated. The AND (or BIT) will generate the condition codes, // but they are different from CMP. + // FIXME: since we're doing a post-processing, use a pseudoinstr here, so + // lowering & isel wouldn't diverge. bool andCC = false; if (ConstantSDNode *RHSC = dyn_cast(RHS)) { if (RHSC->isNullValue() && LHS.hasOneUse() && @@ -782,11 +784,11 @@ SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { case MSP430CC::COND_HS: // Res = SRW & 1, no processing is required break; - case MSP430CC::COND_LO: + case MSP430CC::COND_LO: // Res = ~(SRW & 1) Invert = true; break; - case MSP430CC::COND_NE: + case MSP430CC::COND_NE: if (andCC) { // C = ~Z, thus Res = SRW & 1, no processing is required } else { @@ -794,7 +796,7 @@ SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { Shift = true; } break; - case MSP430CC::COND_E: + case MSP430CC::COND_E: if (andCC) { // C = ~Z, thus Res = ~(SRW & 1) } else { @@ -808,7 +810,7 @@ SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { SDValue One = DAG.getConstant(1, VT); if (Convert) { SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW, - MVT::i16, Flag); + MVT::i16, Flag); if (Shift) // FIXME: somewhere this is turned into a SRL, lower it MSP specific? SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); diff --git a/lib/Target/MSP430/MSP430InstrInfo.td b/lib/Target/MSP430/MSP430InstrInfo.td index 022d171f35b..06a039fd668 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.td +++ b/lib/Target/MSP430/MSP430InstrInfo.td @@ -861,58 +861,60 @@ def CMP16mr : Pseudo<(outs), (ins memsrc:$src1, GR16:$src2), let isCommutable = 1 in { def BIT8rr : Pseudo<(outs), (ins GR8:$src1, GR8:$src2), "bit.b\t{$src2, $src1}", - [(MSP430cmp 0, (and_su GR8:$src1, GR8:$src2)), + [(MSP430cmp (and_su GR8:$src1, GR8:$src2), 0), (implicit SRW)]>; def BIT16rr : Pseudo<(outs), (ins GR16:$src1, GR16:$src2), "bit.w\t{$src2, $src1}", - [(MSP430cmp 0, (and_su GR16:$src1, GR16:$src2)), + [(MSP430cmp (and_su GR16:$src1, GR16:$src2), 0), (implicit SRW)]>; } def BIT8ri : Pseudo<(outs), (ins GR8:$src1, i8imm:$src2), "bit.b\t{$src2, $src1}", - [(MSP430cmp 0, (and_su GR8:$src1, imm:$src2)), + [(MSP430cmp (and_su GR8:$src1, imm:$src2), 0), (implicit SRW)]>; def BIT16ri : Pseudo<(outs), (ins GR16:$src1, i16imm:$src2), "bit.w\t{$src2, $src1}", - [(MSP430cmp 0, (and_su GR16:$src1, imm:$src2)), + [(MSP430cmp (and_su GR16:$src1, imm:$src2), 0), (implicit SRW)]>; def BIT8rm : Pseudo<(outs), (ins GR8:$src1, memdst:$src2), "bit.b\t{$src2, $src1}", - [(MSP430cmp 0, (and_su GR8:$src1, (load addr:$src2))), + [(MSP430cmp (and_su GR8:$src1, (load addr:$src2)), 0), (implicit SRW)]>; def BIT16rm : Pseudo<(outs), (ins GR16:$src1, memdst:$src2), "bit.w\t{$src2, $src1}", - [(MSP430cmp 0, (and_su GR16:$src1, (load addr:$src2))), + [(MSP430cmp (and_su GR16:$src1, (load addr:$src2)), 0), (implicit SRW)]>; def BIT8mr : Pseudo<(outs), (ins memsrc:$src1, GR8:$src2), "bit.b\t{$src2, $src1}", - [(MSP430cmp 0, (and_su (load addr:$src1), GR8:$src2)), + [(MSP430cmp (and_su (load addr:$src1), GR8:$src2), 0), (implicit SRW)]>; def BIT16mr : Pseudo<(outs), (ins memsrc:$src1, GR16:$src2), "bit.w\t{$src2, $src1}", - [(MSP430cmp 0, (and_su (load addr:$src1), GR16:$src2)), + [(MSP430cmp (and_su (load addr:$src1), GR16:$src2), 0), (implicit SRW)]>; def BIT8mi : Pseudo<(outs), (ins memsrc:$src1, i8imm:$src2), "bit.b\t{$src2, $src1}", - [(MSP430cmp 0, (and_su (load addr:$src1), (i8 imm:$src2))), + [(MSP430cmp (and_su (load addr:$src1), (i8 imm:$src2)), 0), (implicit SRW)]>; def BIT16mi : Pseudo<(outs), (ins memsrc:$src1, i16imm:$src2), "bit.w\t{$src2, $src1}", - [(MSP430cmp 0, (and_su (load addr:$src1), (i16 imm:$src2))), + [(MSP430cmp (and_su (load addr:$src1), (i16 imm:$src2)), 0), (implicit SRW)]>; def BIT8mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2), "bit.b\t{$src2, $src1}", - [(MSP430cmp 0, (and_su (i8 (load addr:$src1)), - (load addr:$src2))), + [(MSP430cmp (and_su (i8 (load addr:$src1)), + (load addr:$src2)), + 0), (implicit SRW)]>; def BIT16mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2), "bit.w\t{$src2, $src1}", - [(MSP430cmp 0, (and_su (i16 (load addr:$src1)), - (load addr:$src2))), + [(MSP430cmp (and_su (i16 (load addr:$src1)), + (load addr:$src2)), + 0), (implicit SRW)]>; } // Defs = [SRW] @@ -923,7 +925,8 @@ def BIT16mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2), def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; // anyext -def : Pat<(anyext addr:$src), (MOVZX16rr8 GR8:$src)>; +def : Pat<(i16 (anyext GR8:$src)), + (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>; // truncs def : Pat<(i8 (trunc GR16:$src)), @@ -996,6 +999,6 @@ def : Pat<(store (subc (load addr:$dst), (i8 (load addr:$src))), addr:$dst), // peephole patterns def : Pat<(and GR16:$src, 255), (ZEXT16r GR16:$src)>; -def : Pat<(MSP430cmp 0, (trunc (and_su GR16:$src1, GR16:$src2))), +def : Pat<(MSP430cmp (trunc (and_su GR16:$src1, GR16:$src2)), 0), (BIT8rr (EXTRACT_SUBREG GR16:$src1, subreg_8bit), (EXTRACT_SUBREG GR16:$src2, subreg_8bit))>;