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[mips][micromips] Add predicate 'InMicroMips' at CodeGen patterns for microMIPS instructions

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Differential Revision: http://reviews.llvm.org/D6198


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221780 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic
2014-11-12 13:30:10 +00:00
parent 556578ec0c
commit cb5fadfe6a
2 changed files with 26 additions and 1 deletions
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3
lib/Target/Mips/MicroMipsInstrInfo.td
View File

@@ -510,6 +510,8 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>; def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
} }
let Predicates = [InMicroMips] in {
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MicroMips arbitrary patterns that map to one or more instructions // MicroMips arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@@ -533,6 +535,5 @@ def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
// MicroMips instruction aliases // MicroMips instruction aliases
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [InMicroMips] in {
def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>; def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
} }

24
test/CodeGen/Mips/Fast-ISel/shift.ll Normal file
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@@ -0,0 +1,24 @@
; RUN: llc -march=mipsel -mcpu=mips32r2 -O1 -fast-isel=true -mips-fast-isel -filetype=obj %s -o - \
; RUN: | llvm-objdump -arch mipsel -mcpu=mips32r2 -d - | FileCheck %s
; This test checks that encoding for srl is correct when fast-isel for mips32r2 is used.
%struct.s = type { [4 x i8], i32 }
define i32 @main() nounwind uwtable {
entry:
%foo = alloca %struct.s, align 4
%0 = bitcast %struct.s* %foo to i32*
%bf.load = load i32* %0, align 4
%bf.lshr = lshr i32 %bf.load, 2
%cmp = icmp ne i32 %bf.lshr, 2
br i1 %cmp, label %if.then, label %if.end
if.then:
unreachable
if.end:
ret i32 0
}
; CHECK: srl ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}}