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Have getRegForInlineAsmConstraint return the correct register class when target

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is Mips64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147516 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2012-01-04 02:45:01 +00:00
parent afad0fe59a
commit cb9dd72fdc
3 changed files with 64 additions and 4 deletions
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13
lib/Target/Mips/MipsISelLowering.cpp
View File

@@ -2871,14 +2871,19 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
case 'd': // Address register. Same as 'r' unless generating MIPS16 code. case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
case 'y': // Same as 'r'. Exists for compatibility. case 'y': // Same as 'r'. Exists for compatibility.
case 'r': case 'r':
return std::make_pair(0U, Mips::CPURegsRegisterClass); if (VT == MVT::i32)
return std::make_pair(0U, Mips::CPURegsRegisterClass);
assert(VT == MVT::i64 && "Unexpected type.");
return std::make_pair(0U, Mips::CPU64RegsRegisterClass);
case 'f': case 'f':
if (VT == MVT::f32) if (VT == MVT::f32)
return std::make_pair(0U, Mips::FGR32RegisterClass); return std::make_pair(0U, Mips::FGR32RegisterClass);
if (VT == MVT::f64) if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) if (Subtarget->isFP64bit())
return std::make_pair(0U, Mips::FGR64RegisterClass);
else
return std::make_pair(0U, Mips::AFGR64RegisterClass); return std::make_pair(0U, Mips::AFGR64RegisterClass);
break; }
} }
} }
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);

38
test/CodeGen/Mips/2008-08-01-AsmInline.ll
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@@ -1,4 +1,5 @@
; RUN: llc -march=mips < %s | FileCheck %s ; RUN: llc -march=mips < %s | FileCheck %s
; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s
%struct.DWstruct = type { i32, i32 } %struct.DWstruct = type { i32, i32 }
@@ -13,3 +14,40 @@ entry:
%res = add i32 %asmresult, %asmresult1 %res = add i32 %asmresult, %asmresult1
ret i32 %res ret i32 %res
} }
@gi2 = external global i32
@gi1 = external global i32
@gi0 = external global i32
@gf0 = external global float
@gf1 = external global float
@gd0 = external global double
@gd1 = external global double
define void @foo0() nounwind {
entry:
; CHECK: addu
%0 = load i32* @gi1, align 4
%1 = load i32* @gi0, align 4
%2 = tail call i32 asm "addu $0, $1, $2", "=r,r,r"(i32 %0, i32 %1) nounwind
store i32 %2, i32* @gi2, align 4
ret void
}
define void @foo2() nounwind {
entry:
; CHECK: neg.s
%0 = load float* @gf1, align 4
%1 = tail call float asm "neg.s $0, $1", "=f,f"(float %0) nounwind
store float %1, float* @gf0, align 4
ret void
}
define void @foo3() nounwind {
entry:
; CHECK: neg.d
%0 = load double* @gd1, align 8
%1 = tail call double asm "neg.d $0, $1", "=f,f"(double %0) nounwind
store double %1, double* @gd0, align 8
ret void
}

17
test/CodeGen/Mips/inlineasm64.ll Normal file
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@@ -0,0 +1,17 @@
; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s
@gl2 = external global i64
@gl1 = external global i64
@gl0 = external global i64
define void @foo1() nounwind {
entry:
; CHECK: foo1
; CHECK: daddu
%0 = load i64* @gl1, align 8
%1 = load i64* @gl0, align 8
%2 = tail call i64 asm "daddu $0, $1, $2", "=r,r,r"(i64 %0, i64 %1) nounwind
store i64 %2, i64* @gl2, align 8
ret void
}