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[FastISel][X86] Use INC/DEC when possible for {sadd|ssub}.with.overflow intrinsics.
This is a small peephole optimization to emit INC/DEC when possible. Fixes <rdar://problem/17952308>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215230 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
parent
6d56b950a9
commit
cbda4b32c6
@ -2374,15 +2374,19 @@ bool X86FastISel::FastLowerIntrinsicCall(const IntrinsicInst *II) {
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isCommutativeIntrinsic(II))
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std::swap(LHS, RHS);
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bool UseIncDec = false;
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if (isa<ConstantInt>(RHS) && cast<ConstantInt>(RHS)->isOne())
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UseIncDec = true;
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unsigned BaseOpc, CondOpc;
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switch (II->getIntrinsicID()) {
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default: llvm_unreachable("Unexpected intrinsic!");
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case Intrinsic::sadd_with_overflow:
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BaseOpc = ISD::ADD; CondOpc = X86::SETOr; break;
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BaseOpc = UseIncDec ? X86ISD::INC : ISD::ADD; CondOpc = X86::SETOr; break;
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case Intrinsic::uadd_with_overflow:
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BaseOpc = ISD::ADD; CondOpc = X86::SETBr; break;
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case Intrinsic::ssub_with_overflow:
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BaseOpc = ISD::SUB; CondOpc = X86::SETOr; break;
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BaseOpc = UseIncDec ? X86ISD::DEC : ISD::SUB; CondOpc = X86::SETOr; break;
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case Intrinsic::usub_with_overflow:
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BaseOpc = ISD::SUB; CondOpc = X86::SETBr; break;
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case Intrinsic::smul_with_overflow:
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@ -2398,9 +2402,24 @@ bool X86FastISel::FastLowerIntrinsicCall(const IntrinsicInst *II) {
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unsigned ResultReg = 0;
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// Check if we have an immediate version.
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if (auto const *C = dyn_cast<ConstantInt>(RHS)) {
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ResultReg = FastEmit_ri(VT, VT, BaseOpc, LHSReg, LHSIsKill,
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C->getZExtValue());
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if (const auto *CI = dyn_cast<ConstantInt>(RHS)) {
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static const unsigned Opc[2][2][4] = {
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{ { X86::INC8r, X86::INC16r, X86::INC32r, X86::INC64r },
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{ X86::DEC8r, X86::DEC16r, X86::DEC32r, X86::DEC64r } },
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{ { X86::INC8r, X86::INC64_16r, X86::INC64_32r, X86::INC64r },
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{ X86::DEC8r, X86::DEC64_16r, X86::DEC64_32r, X86::DEC64r } }
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};
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if (UseIncDec) {
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ResultReg = createResultReg(TLI.getRegClassFor(VT));
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bool Is64Bit = Subtarget->is64Bit();
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bool IsDec = BaseOpc == X86ISD::DEC;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(Opc[Is64Bit][IsDec][VT.SimpleTy-MVT::i8]), ResultReg)
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.addReg(LHSReg, getKillRegState(LHSIsKill));
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} else
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ResultReg = FastEmit_ri(VT, VT, BaseOpc, LHSReg, LHSIsKill,
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CI->getZExtValue());
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}
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unsigned RHSReg;
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@ -67,16 +67,48 @@ entry:
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ret i1 %obit
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}
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; SADDO reg, imm | imm, reg
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; FIXME: INC isn't supported in FastISel yet
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define zeroext i1 @saddo.i64imm1(i64 %v1, i64* %res) {
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; SADDO reg, 1 | INC
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define zeroext i1 @saddo.inc.i8(i8 %v1, i8* %res) {
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entry:
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; DAG-LABEL: saddo.i64imm1
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; DAG: incq %rdi
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; DAG-NEXT: seto %al
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; FAST-LABEL: saddo.i64imm1
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; FAST: addq $1, %rdi
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; FAST-NEXT: seto %al
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; CHECK-LABEL: saddo.inc.i8
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; CHECK: incb %dil
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; CHECK-NEXT: seto %al
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%t = call {i8, i1} @llvm.sadd.with.overflow.i8(i8 %v1, i8 1)
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%val = extractvalue {i8, i1} %t, 0
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%obit = extractvalue {i8, i1} %t, 1
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store i8 %val, i8* %res
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ret i1 %obit
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}
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define zeroext i1 @saddo.inc.i16(i16 %v1, i16* %res) {
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entry:
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; CHECK-LABEL: saddo.inc.i16
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; CHECK: incw %di
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; CHECK-NEXT: seto %al
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%t = call {i16, i1} @llvm.sadd.with.overflow.i16(i16 %v1, i16 1)
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%val = extractvalue {i16, i1} %t, 0
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%obit = extractvalue {i16, i1} %t, 1
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store i16 %val, i16* %res
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ret i1 %obit
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}
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define zeroext i1 @saddo.inc.i32(i32 %v1, i32* %res) {
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entry:
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; CHECK-LABEL: saddo.inc.i32
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; CHECK: incl %edi
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; CHECK-NEXT: seto %al
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 1)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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define zeroext i1 @saddo.inc.i64(i64 %v1, i64* %res) {
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entry:
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; CHECK-LABEL: saddo.inc.i64
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; CHECK: incq %rdi
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; CHECK-NEXT: seto %al
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 1)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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@ -84,17 +116,18 @@ entry:
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ret i1 %obit
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}
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; SADDO reg, imm | imm, reg
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; FIXME: DAG doesn't optimize immediates on the LHS.
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define zeroext i1 @saddo.i64imm2(i64 %v1, i64* %res) {
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define zeroext i1 @saddo.i64imm1(i64 %v1, i64* %res) {
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entry:
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; DAG-LABEL: saddo.i64imm2
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; DAG-LABEL: saddo.i64imm1
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; DAG: mov
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; DAG-NEXT: addq
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; DAG-NEXT: seto
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; FAST-LABEL: saddo.i64imm2
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; FAST: addq $1, %rdi
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; FAST-LABEL: saddo.i64imm1
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; FAST: addq $2, %rdi
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; FAST-NEXT: seto %al
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 1, i64 %v1)
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 2, i64 %v1)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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@ -102,12 +135,12 @@ entry:
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}
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; Check boundary conditions for large immediates.
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define zeroext i1 @saddo.i64imm3(i64 %v1, i64* %res) {
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define zeroext i1 @saddo.i64imm2(i64 %v1, i64* %res) {
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entry:
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; DAG-LABEL: saddo.i64imm3
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; DAG-LABEL: saddo.i64imm2
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; DAG: addq $-2147483648, %rdi
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; DAG-NEXT: seto %al
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; FAST-LABEL: saddo.i64imm3
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; FAST-LABEL: saddo.i64imm2
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; FAST: addq $-2147483648, %rdi
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; FAST-NEXT: seto %al
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 -2147483648)
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@ -117,13 +150,13 @@ entry:
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ret i1 %obit
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}
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define zeroext i1 @saddo.i64imm4(i64 %v1, i64* %res) {
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define zeroext i1 @saddo.i64imm3(i64 %v1, i64* %res) {
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entry:
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; DAG-LABEL: saddo.i64imm4
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; DAG-LABEL: saddo.i64imm3
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; DAG: movabsq $-21474836489, %[[REG:[a-z]+]]
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; DAG-NEXT: addq %rdi, %[[REG]]
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; DAG-NEXT: seto
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; FAST-LABEL: saddo.i64imm4
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; FAST-LABEL: saddo.i64imm3
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; FAST: movabsq $-21474836489, %[[REG:[a-z]+]]
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; FAST-NEXT: addq %rdi, %[[REG]]
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; FAST-NEXT: seto
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@ -134,12 +167,12 @@ entry:
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ret i1 %obit
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}
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define zeroext i1 @saddo.i64imm5(i64 %v1, i64* %res) {
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define zeroext i1 @saddo.i64imm4(i64 %v1, i64* %res) {
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entry:
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; DAG-LABEL: saddo.i64imm5
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; DAG-LABEL: saddo.i64imm4
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; DAG: addq $2147483647, %rdi
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; DAG-NEXT: seto
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; FAST-LABEL: saddo.i64imm5
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; FAST-LABEL: saddo.i64imm4
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; FAST: addq $2147483647, %rdi
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; FAST-NEXT: seto
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 2147483647)
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@ -150,13 +183,13 @@ entry:
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}
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; TODO: FastISel shouldn't use movabsq.
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define zeroext i1 @saddo.i64imm6(i64 %v1, i64* %res) {
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define zeroext i1 @saddo.i64imm5(i64 %v1, i64* %res) {
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entry:
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; DAG-LABEL: saddo.i64imm6
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; DAG-LABEL: saddo.i64imm5
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; DAG: movl $2147483648, %ecx
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; DAG: addq %rdi, %rcx
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; DAG-NEXT: seto
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; FAST-LABEL: saddo.i64imm6
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; FAST-LABEL: saddo.i64imm5
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; FAST: movabsq $2147483648, %[[REG:[a-z]+]]
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; FAST: addq %rdi, %[[REG]]
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; FAST-NEXT: seto
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