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Fix FreeBench/fourinarow with the dag isel, by not adding a bogus result

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to SHIFT_PARTS nodes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23151 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-08-30 17:21:17 +00:00
parent 2501d5e29c
commit cc0675a4be
1 changed files with 1 additions and 4 deletions
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5
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -2388,10 +2388,7 @@ void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
Ops.push_back(LHSL);
Ops.push_back(LHSH);
Ops.push_back(Amt);
std::vector<MVT::ValueType> VTs;
VTs.push_back(LHSL.getValueType());
VTs.push_back(LHSH.getValueType());
VTs.push_back(Amt.getValueType());
std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
Lo = DAG.getNode(NodeOp, VTs, Ops);
Hi = Lo.getValue(1);
}