6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-03-09 11:32:48 +00:00
Code Issues Projects Releases Wiki Activity

remove MachineOpCode typedef.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45679 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-01-07 02:48:55 +00:00
parent ba6da5d5b7
commit cc8cd0cbf1
8 changed files with 8 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
include/llvm/Target/TargetInstrInfo.h
View File

@ -32,12 +32,6 @@ class SelectionDAG;
template<class T> class SmallVectorImpl;
//===----------------------------------------------------------------------===//
// Data types used to define information about a single machine instruction
//===----------------------------------------------------------------------===//
typedef short MachineOpCode;
//===----------------------------------------------------------------------===//
// struct TargetInstrDescriptor:
// Predefined information about each machine instruction.

2
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -52,7 +52,7 @@ const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
///
bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg) const {
MachineOpCode oc = MI.getOpcode();
unsigned oc = MI.getOpcode();
switch (oc) {
default:
return false;

2
lib/Target/Alpha/AlphaInstrInfo.cpp
View File

@ -26,7 +26,7 @@ AlphaInstrInfo::AlphaInstrInfo()
bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
MachineOpCode oc = MI.getOpcode();
unsigned oc = MI.getOpcode();
if (oc == Alpha::BISr ||
oc == Alpha::CPYSS ||
oc == Alpha::CPYST ||

4
lib/Target/CellSPU/SPUInstrInfo.cpp
View File

@ -225,7 +225,7 @@ SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
unsigned SrcReg, bool isKill, int FrameIdx,
const TargetRegisterClass *RC) const
{
MachineOpCode opc;
unsigned opc;
if (RC == SPU::GPRCRegisterClass) {
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
? SPU::STQDr128
@ -308,7 +308,7 @@ SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const
{
MachineOpCode opc;
unsigned opc;
if (RC == SPU::GPRCRegisterClass) {
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
? SPU::LQDr128

2
lib/Target/IA64/IA64InstrInfo.cpp
View File

@ -27,7 +27,7 @@ IA64InstrInfo::IA64InstrInfo()
bool IA64InstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
MachineOpCode oc = MI.getOpcode();
unsigned oc = MI.getOpcode();
if (oc == IA64::MOV || oc == IA64::FMOV) {
// TODO: this doesn't detect predicate moves
assert(MI.getNumOperands() >= 2 &&

2
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -37,7 +37,7 @@ const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
MachineOpCode oc = MI.getOpcode();
unsigned oc = MI.getOpcode();
if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
assert(MI.getNumOperands() >= 3 &&

2
lib/Target/X86/X86InstrInfo.cpp
View File

@ -636,7 +636,7 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
MachineOpCode oc = MI.getOpcode();
unsigned oc = MI.getOpcode();
if (oc == X86::MOV8rr || oc == X86::MOV16rr ||
oc == X86::MOV32rr || oc == X86::MOV64rr ||
oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||

2
lib/Target/X86/X86InstrInfo.h
View File

@ -367,7 +367,7 @@ public:
unsigned char getBaseOpcodeFor(const TargetInstrDescriptor *TID) const {
return TID->TSFlags >> X86II::OpcodeShift;
}
unsigned char getBaseOpcodeFor(MachineOpCode Opcode) const {
unsigned char getBaseOpcodeFor(unsigned Opcode) const {
return getBaseOpcodeFor(&get(Opcode));
}