diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index d47ee740b63..d8aff40fa1c 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -32,12 +32,6 @@ class SelectionDAG;
 
 template<class T> class SmallVectorImpl;
 
-//===----------------------------------------------------------------------===//
-// Data types used to define information about a single machine instruction
-//===----------------------------------------------------------------------===//
-
-typedef short MachineOpCode;
-
 //===----------------------------------------------------------------------===//
 // struct TargetInstrDescriptor:
 //  Predefined information about each machine instruction.
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 35226379e1c..b291d19d865 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -52,7 +52,7 @@ const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
 ///
 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
                                unsigned &SrcReg, unsigned &DstReg) const {
-  MachineOpCode oc = MI.getOpcode();
+  unsigned oc = MI.getOpcode();
   switch (oc) {
   default:
     return false;
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index abd7e33a694..53d71048703 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -26,7 +26,7 @@ AlphaInstrInfo::AlphaInstrInfo()
 bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
                                  unsigned& sourceReg,
                                  unsigned& destReg) const {
-  MachineOpCode oc = MI.getOpcode();
+  unsigned oc = MI.getOpcode();
   if (oc == Alpha::BISr   || 
       oc == Alpha::CPYSS  || 
       oc == Alpha::CPYST  ||
diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index e9b263f0c9d..e72cd1243c5 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -225,7 +225,7 @@ SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                      unsigned SrcReg, bool isKill, int FrameIdx,
                                      const TargetRegisterClass *RC) const
 {
-  MachineOpCode opc;
+  unsigned opc;
   if (RC == SPU::GPRCRegisterClass) {
     opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
       ? SPU::STQDr128
@@ -308,7 +308,7 @@ SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                         unsigned DestReg, int FrameIdx,
                                         const TargetRegisterClass *RC) const
 {
-  MachineOpCode opc;
+  unsigned opc;
   if (RC == SPU::GPRCRegisterClass) {
     opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
       ? SPU::LQDr128
diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp
index f33b5da9ed7..2ba2c8fe1d6 100644
--- a/lib/Target/IA64/IA64InstrInfo.cpp
+++ b/lib/Target/IA64/IA64InstrInfo.cpp
@@ -27,7 +27,7 @@ IA64InstrInfo::IA64InstrInfo()
 bool IA64InstrInfo::isMoveInstr(const MachineInstr& MI,
                                unsigned& sourceReg,
                                unsigned& destReg) const {
-  MachineOpCode oc = MI.getOpcode();
+  unsigned oc = MI.getOpcode();
   if (oc == IA64::MOV || oc == IA64::FMOV) {
   // TODO: this doesn't detect predicate moves
      assert(MI.getNumOperands() >= 2 &&
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 4d404a547ff..47e28710176 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -37,7 +37,7 @@ const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
                                unsigned& sourceReg,
                                unsigned& destReg) const {
-  MachineOpCode oc = MI.getOpcode();
+  unsigned oc = MI.getOpcode();
   if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
       oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
     assert(MI.getNumOperands() >= 3 &&
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index d79c1edf9f4..eb455ca8da6 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -636,7 +636,7 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
                                unsigned& sourceReg,
                                unsigned& destReg) const {
-  MachineOpCode oc = MI.getOpcode();
+  unsigned oc = MI.getOpcode();
   if (oc == X86::MOV8rr || oc == X86::MOV16rr ||
       oc == X86::MOV32rr || oc == X86::MOV64rr ||
       oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||
diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index ccee43d6bba..c0aefb41477 100644
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -367,7 +367,7 @@ public:
   unsigned char getBaseOpcodeFor(const TargetInstrDescriptor *TID) const {
     return TID->TSFlags >> X86II::OpcodeShift;
   }
-  unsigned char getBaseOpcodeFor(MachineOpCode Opcode) const {
+  unsigned char getBaseOpcodeFor(unsigned Opcode) const {
     return getBaseOpcodeFor(&get(Opcode));
   }