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[AArch32] Add support for FP rounding operations for ARMv8/AArch32.
Phabricator Revision: http://reviews.llvm.org/D4935 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215772 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
parent
4a8a0f2132
commit
cc921d6f41
@ -869,6 +869,18 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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}
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}
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// ARMv8 implements a lot of rounding-like FP operations.
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if (Subtarget->hasV8Ops()) {
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static MVT RoundingTypes[] = {MVT::f32, MVT::f64};
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for (const auto Ty : RoundingTypes) {
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setOperationAction(ISD::FFLOOR, Ty, Legal);
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setOperationAction(ISD::FCEIL, Ty, Legal);
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setOperationAction(ISD::FROUND, Ty, Legal);
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setOperationAction(ISD::FTRUNC, Ty, Legal);
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setOperationAction(ISD::FNEARBYINT, Ty, Legal);
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setOperationAction(ISD::FRINT, Ty, Legal);
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}
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}
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// We have target-specific dag combine patterns for the following nodes:
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// ARMISD::VMOVRRD - No need to call setTargetDAGCombine
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setTargetDAGCombine(ISD::ADD);
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@ -691,18 +691,20 @@ def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
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let D = VFPNeonA8Domain;
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}
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multiclass vrint_inst_zrx<string opc, bit op, bit op2> {
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multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> {
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def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
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(outs SPR:$Sd), (ins SPR:$Sm),
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NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
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[]>, Requires<[HasFPARMv8]> {
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[(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
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Requires<[HasFPARMv8]> {
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let Inst{7} = op2;
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let Inst{16} = op;
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}
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def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,
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(outs DPR:$Dd), (ins DPR:$Dm),
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NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
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[]>, Requires<[HasFPARMv8, HasDPVFP]> {
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[(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
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Requires<[HasFPARMv8, HasDPVFP]> {
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let Inst{7} = op2;
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let Inst{16} = op;
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}
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@ -715,22 +717,25 @@ multiclass vrint_inst_zrx<string opc, bit op, bit op2> {
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Requires<[HasFPARMv8,HasDPVFP]>;
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}
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defm VRINTZ : vrint_inst_zrx<"z", 0, 1>;
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defm VRINTR : vrint_inst_zrx<"r", 0, 0>;
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defm VRINTX : vrint_inst_zrx<"x", 1, 0>;
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defm VRINTZ : vrint_inst_zrx<"z", 0, 1, ftrunc>;
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defm VRINTR : vrint_inst_zrx<"r", 0, 0, fnearbyint>;
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defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>;
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multiclass vrint_inst_anpm<string opc, bits<2> rm> {
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multiclass vrint_inst_anpm<string opc, bits<2> rm,
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SDPatternOperator node = null_frag> {
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let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
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def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,
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(outs SPR:$Sd), (ins SPR:$Sm),
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NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
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[]>, Requires<[HasFPARMv8]> {
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[(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
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Requires<[HasFPARMv8]> {
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let Inst{17-16} = rm;
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}
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def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0,
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(outs DPR:$Dd), (ins DPR:$Dm),
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NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),
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[]>, Requires<[HasFPARMv8, HasDPVFP]> {
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[(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
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Requires<[HasFPARMv8, HasDPVFP]> {
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let Inst{17-16} = rm;
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}
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}
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@ -743,10 +748,10 @@ multiclass vrint_inst_anpm<string opc, bits<2> rm> {
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Requires<[HasFPARMv8,HasDPVFP]>;
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}
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defm VRINTA : vrint_inst_anpm<"a", 0b00>;
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defm VRINTA : vrint_inst_anpm<"a", 0b00, frnd>;
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defm VRINTN : vrint_inst_anpm<"n", 0b01>;
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defm VRINTP : vrint_inst_anpm<"p", 0b10>;
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defm VRINTM : vrint_inst_anpm<"m", 0b11>;
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defm VRINTP : vrint_inst_anpm<"p", 0b10, fceil>;
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defm VRINTM : vrint_inst_anpm<"m", 0b11, ffloor>;
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def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
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(outs DPR:$Dd), (ins DPR:$Dm),
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110
test/CodeGen/ARM/arm32-rounding.ll
Normal file
110
test/CodeGen/ARM/arm32-rounding.ll
Normal file
@ -0,0 +1,110 @@
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; RUN: llc < %s -mtriple=armv8-linux-gnueabihf -mattr=+fp-armv8 | FileCheck %s
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; CHECK-LABEL: test1
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; CHECK: vrintm.f32
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define float @test1(float %a) {
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entry:
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%call = call float @floorf(float %a) nounwind readnone
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ret float %call
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}
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; CHECK-LABEL: test2
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; CHECK: vrintm.f64
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define double @test2(double %a) {
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entry:
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%call = call double @floor(double %a) nounwind readnone
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ret double %call
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}
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; CHECK-LABEL: test3
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; CHECK: vrintp.f32
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define float @test3(float %a) {
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entry:
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%call = call float @ceilf(float %a) nounwind readnone
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ret float %call
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}
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; CHECK-LABEL: test4
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; CHECK: vrintp.f64
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define double @test4(double %a) {
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entry:
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%call = call double @ceil(double %a) nounwind readnone
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ret double %call
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}
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; CHECK-LABEL: test5
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; CHECK: vrinta.f32
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define float @test5(float %a) {
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entry:
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%call = call float @roundf(float %a) nounwind readnone
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ret float %call
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}
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; CHECK-LABEL: test6
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; CHECK: vrinta.f64
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define double @test6(double %a) {
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entry:
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%call = call double @round(double %a) nounwind readnone
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ret double %call
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}
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; CHECK-LABEL: test7
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; CHECK: vrintz.f32
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define float @test7(float %a) {
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entry:
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%call = call float @truncf(float %a) nounwind readnone
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ret float %call
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}
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; CHECK-LABEL: test8
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; CHECK: vrintz.f64
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define double @test8(double %a) {
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entry:
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%call = call double @trunc(double %a) nounwind readnone
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ret double %call
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}
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; CHECK-LABEL: test9
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; CHECK: vrintr.f32
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define float @test9(float %a) {
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entry:
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%call = call float @nearbyintf(float %a) nounwind readnone
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ret float %call
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}
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; CHECK-LABEL: test10
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; CHECK: vrintr.f64
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define double @test10(double %a) {
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entry:
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%call = call double @nearbyint(double %a) nounwind readnone
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ret double %call
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}
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; CHECK-LABEL: test11
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; CHECK: vrintx.f32
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define float @test11(float %a) {
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entry:
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%call = call float @rintf(float %a) nounwind readnone
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ret float %call
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}
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; CHECK-LABEL: test12
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; CHECK: vrintx.f64
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define double @test12(double %a) {
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entry:
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%call = call double @rint(double %a) nounwind readnone
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ret double %call
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}
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declare float @floorf(float) nounwind readnone
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declare double @floor(double) nounwind readnone
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declare float @ceilf(float) nounwind readnone
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declare double @ceil(double) nounwind readnone
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declare float @roundf(float) nounwind readnone
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declare double @round(double) nounwind readnone
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declare float @truncf(float) nounwind readnone
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declare double @trunc(double) nounwind readnone
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declare float @nearbyintf(float) nounwind readnone
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declare double @nearbyint(double) nounwind readnone
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declare float @rintf(float) nounwind readnone
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declare double @rint(double) nounwind readnone
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