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Promote vector AND, OR, and XOR

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27632 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-04-12 21:20:24 +00:00
parent 67263ba611
commit cc9876124e
1 changed files with 27 additions and 0 deletions
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27
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -2076,6 +2076,25 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), Ops);
break;
}
case TargetLowering::Promote: {
switch (Node->getOpcode()) {
default: assert(0 && "Do not know how to promote this BinOp!");
case ISD::AND:
case ISD::OR:
case ISD::XOR: {
MVT::ValueType OVT = Node->getValueType(0);
MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
// Bit convert each of the values to the new type.
Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
// Bit convert the result back the original type.
Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
break;
}
}
}
}
break;
@ -2953,6 +2972,14 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
case ISD::AND:
case ISD::OR:
case ISD::XOR:
// The input may have strange things in the top bits of the registers, but
// these operations don't care. They may have weird bits going out, but
// that too is okay if they are integer operations.
Tmp1 = PromoteOp(Node->getOperand(0));
Tmp2 = PromoteOp(Node->getOperand(1));
assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
break;
case ISD::ADD:
case ISD::SUB:
case ISD::MUL: