6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-10-31 08:16:47 +00:00
Code Issues Projects Releases Wiki Activity

Make TargetRegisterClasses non-virtual by making the only virtual function a function pointer.

Browse Source 
This allows us to make TRC non-polymorphic and value-initializable, eliminating a huge static
initializer and a ton of cruft from the generated code.

Shrinks ARMBaseRegisterInfo.o by ~100k.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151806 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer
2012-03-01 13:37:55 +00:00
parent 54d42a740d
commit ccc8d3ba06
3 changed files with 45 additions and 60 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
include/llvm/Target/TargetRegisterInfo.h
View File

@@ -38,23 +38,14 @@ public:
typedef const unsigned* const_iterator;
typedef const MVT::SimpleValueType* vt_iterator;
typedef const TargetRegisterClass* const * sc_iterator;
private:
virtual void anchor();
// Instance variables filled by tablegen, do not use!
const MCRegisterClass *MC;
const vt_iterator VTs;
const unsigned *SubClassMask;
const sc_iterator SuperClasses;
const sc_iterator SuperRegClasses;
public:
TargetRegisterClass(const MCRegisterClass *MC,
const MVT::SimpleValueType *vts,
const unsigned *subcm,
const TargetRegisterClass * const *supcs,
const TargetRegisterClass * const *superregcs)
: MC(MC), VTs(vts), SubClassMask(subcm), SuperClasses(supcs),
SuperRegClasses(superregcs) {}
virtual ~TargetRegisterClass() {} // Allow subclasses
ArrayRef<unsigned> (*OrderFunc)(const MachineFunction&);
/// getID() - Return the register class ID number.
///
@@ -199,9 +190,8 @@ public:
///
/// By default, this method returns all registers in the class.
///
virtual
ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const {
return makeArrayRef(begin(), getNumRegs());
return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
}
};