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Fix bug involving bool arguments to binary operators.

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Fix typo in comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14684 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke 2004-07-08 08:08:10 +00:00
parent 2a9f539168
commit ccdd70a5c0
4 changed files with 8 additions and 8 deletions
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4
lib/Target/Sparc/InstSelectSimple.cpp
View File

@ -904,7 +904,7 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
}
switch (getClass (I.getType ())) {
switch (getClassB (I.getType ())) {
case cByte:
if (I.getType ()->isSigned ()) { // add byte
BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
@ -926,7 +926,7 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
}
break;
case cInt:
// Nothing todo here.
// Nothing to do here.
break;
case cLong:
// Only support and, or, xor.

4
lib/Target/Sparc/SparcV8ISelSimple.cpp
View File

@ -904,7 +904,7 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
}
switch (getClass (I.getType ())) {
switch (getClassB (I.getType ())) {
case cByte:
if (I.getType ()->isSigned ()) { // add byte
BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
@ -926,7 +926,7 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
}
break;
case cInt:
// Nothing todo here.
// Nothing to do here.
break;
case cLong:
// Only support and, or, xor.

4
lib/Target/SparcV8/InstSelectSimple.cpp
View File

@ -904,7 +904,7 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
}
switch (getClass (I.getType ())) {
switch (getClassB (I.getType ())) {
case cByte:
if (I.getType ()->isSigned ()) { // add byte
BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
@ -926,7 +926,7 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
}
break;
case cInt:
// Nothing todo here.
// Nothing to do here.
break;
case cLong:
// Only support and, or, xor.

4
lib/Target/SparcV8/SparcV8ISelSimple.cpp
View File

@ -904,7 +904,7 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
}
switch (getClass (I.getType ())) {
switch (getClassB (I.getType ())) {
case cByte:
if (I.getType ()->isSigned ()) { // add byte
BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
@ -926,7 +926,7 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
}
break;
case cInt:
// Nothing todo here.
// Nothing to do here.
break;
case cLong:
// Only support and, or, xor.