mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-10-31 08:16:47 +00:00
[FastISel][X86] Remove no longer needed functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213051 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
@@ -126,10 +126,6 @@ private:
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bool X86SelectFPExt(const Instruction *I);
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bool X86SelectFPExt(const Instruction *I);
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bool X86SelectFPTrunc(const Instruction *I);
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bool X86SelectFPTrunc(const Instruction *I);
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bool X86SelectCall(const Instruction *I);
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bool DoSelectCall(const Instruction *I, const char *MemIntName);
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const X86InstrInfo *getInstrInfo() const {
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const X86InstrInfo *getInstrInfo() const {
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return getTargetMachine()->getInstrInfo();
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return getTargetMachine()->getInstrInfo();
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}
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}
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@@ -2636,25 +2632,6 @@ bool X86FastISel::FastLowerArguments() {
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return true;
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return true;
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}
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}
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bool X86FastISel::X86SelectCall(const Instruction *I) {
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const CallInst *CI = cast<CallInst>(I);
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const Value *Callee = CI->getCalledValue();
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// Can't handle inline asm yet.
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if (isa<InlineAsm>(Callee))
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return false;
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// Skip intrinsic calls - we already handled these.
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if (isa<IntrinsicInst>(CI))
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return false;
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// Allow SelectionDAG isel to handle tail calls.
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if (cast<CallInst>(I)->isTailCall())
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return false;
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return DoSelectCall(I, nullptr);
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}
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static unsigned computeBytesPoppedByCallee(const X86Subtarget *Subtarget,
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static unsigned computeBytesPoppedByCallee(const X86Subtarget *Subtarget,
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CallingConv::ID CC,
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CallingConv::ID CC,
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ImmutableCallSite *CS) {
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ImmutableCallSite *CS) {
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@@ -2672,443 +2649,6 @@ static unsigned computeBytesPoppedByCallee(const X86Subtarget *Subtarget,
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return 4;
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return 4;
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}
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}
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// Select either a call, or an llvm.memcpy/memmove/memset intrinsic
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bool X86FastISel::DoSelectCall(const Instruction *I, const char *MemIntName) {
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const CallInst *CI = cast<CallInst>(I);
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const Value *Callee = CI->getCalledValue();
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// Handle only C and fastcc calling conventions for now.
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ImmutableCallSite CS(CI);
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CallingConv::ID CC = CS.getCallingConv();
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bool isWin64 = Subtarget->isCallingConvWin64(CC);
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if (CC != CallingConv::C && CC != CallingConv::Fast &&
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CC != CallingConv::X86_FastCall && CC != CallingConv::X86_64_Win64 &&
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CC != CallingConv::X86_64_SysV)
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return false;
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// fastcc with -tailcallopt is intended to provide a guaranteed
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// tail call optimization. Fastisel doesn't know how to do that.
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if (CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt)
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return false;
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PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
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FunctionType *FTy = cast<FunctionType>(PT->getElementType());
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bool isVarArg = FTy->isVarArg();
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// Don't know how to handle Win64 varargs yet. Nothing special needed for
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// x86-32. Special handling for x86-64 is implemented.
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if (isVarArg && isWin64)
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return false;
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// Don't know about inalloca yet.
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if (CS.hasInAllocaArgument())
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return false;
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// Fast-isel doesn't know about callee-pop yet.
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if (X86::isCalleePop(CC, Subtarget->is64Bit(), isVarArg,
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TM.Options.GuaranteedTailCallOpt))
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return false;
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// Check whether the function can return without sret-demotion.
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SmallVector<ISD::OutputArg, 4> Outs;
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GetReturnInfo(I->getType(), CS.getAttributes(), Outs, TLI);
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bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
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*FuncInfo.MF, FTy->isVarArg(),
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Outs, FTy->getContext());
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if (!CanLowerReturn)
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return false;
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// Materialize callee address in a register. FIXME: GV address can be
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// handled with a CALLpcrel32 instead.
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X86AddressMode CalleeAM;
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if (!X86SelectCallAddress(Callee, CalleeAM))
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return false;
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unsigned CalleeOp = 0;
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const GlobalValue *GV = nullptr;
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if (CalleeAM.GV != nullptr) {
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GV = CalleeAM.GV;
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} else if (CalleeAM.Base.Reg != 0) {
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CalleeOp = CalleeAM.Base.Reg;
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} else
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return false;
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// Deal with call operands first.
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SmallVector<const Value *, 8> ArgVals;
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SmallVector<unsigned, 8> Args;
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SmallVector<MVT, 8> ArgVTs;
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SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
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unsigned arg_size = CS.arg_size();
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Args.reserve(arg_size);
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ArgVals.reserve(arg_size);
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ArgVTs.reserve(arg_size);
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ArgFlags.reserve(arg_size);
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for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
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i != e; ++i) {
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// If we're lowering a mem intrinsic instead of a regular call, skip the
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// last two arguments, which should not passed to the underlying functions.
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if (MemIntName && e-i <= 2)
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break;
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Value *ArgVal = *i;
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ISD::ArgFlagsTy Flags;
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unsigned AttrInd = i - CS.arg_begin() + 1;
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if (CS.paramHasAttr(AttrInd, Attribute::SExt))
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Flags.setSExt();
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if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
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Flags.setZExt();
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if (CS.paramHasAttr(AttrInd, Attribute::ByVal)) {
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PointerType *Ty = cast<PointerType>(ArgVal->getType());
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Type *ElementTy = Ty->getElementType();
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unsigned FrameSize = DL.getTypeAllocSize(ElementTy);
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unsigned FrameAlign = CS.getParamAlignment(AttrInd);
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if (!FrameAlign)
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FrameAlign = TLI.getByValTypeAlignment(ElementTy);
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Flags.setByVal();
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Flags.setByValSize(FrameSize);
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Flags.setByValAlign(FrameAlign);
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if (!IsMemcpySmall(FrameSize))
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return false;
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}
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if (CS.paramHasAttr(AttrInd, Attribute::InReg))
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Flags.setInReg();
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if (CS.paramHasAttr(AttrInd, Attribute::Nest))
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Flags.setNest();
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// If this is an i1/i8/i16 argument, promote to i32 to avoid an extra
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// instruction. This is safe because it is common to all fastisel supported
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// calling conventions on x86.
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if (ConstantInt *CI = dyn_cast<ConstantInt>(ArgVal)) {
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if (CI->getBitWidth() == 1 || CI->getBitWidth() == 8 ||
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CI->getBitWidth() == 16) {
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if (Flags.isSExt())
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ArgVal = ConstantExpr::getSExt(CI,Type::getInt32Ty(CI->getContext()));
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else
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ArgVal = ConstantExpr::getZExt(CI,Type::getInt32Ty(CI->getContext()));
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}
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}
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unsigned ArgReg;
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// Passing bools around ends up doing a trunc to i1 and passing it.
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// Codegen this as an argument + "and 1".
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if (ArgVal->getType()->isIntegerTy(1) && isa<TruncInst>(ArgVal) &&
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cast<TruncInst>(ArgVal)->getParent() == I->getParent() &&
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ArgVal->hasOneUse()) {
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ArgVal = cast<TruncInst>(ArgVal)->getOperand(0);
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ArgReg = getRegForValue(ArgVal);
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if (ArgReg == 0) return false;
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MVT ArgVT;
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if (!isTypeLegal(ArgVal->getType(), ArgVT)) return false;
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ArgReg = FastEmit_ri(ArgVT, ArgVT, ISD::AND, ArgReg,
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ArgVal->hasOneUse(), 1);
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} else {
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ArgReg = getRegForValue(ArgVal);
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}
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if (ArgReg == 0) return false;
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Type *ArgTy = ArgVal->getType();
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MVT ArgVT;
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if (!isTypeLegal(ArgTy, ArgVT))
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return false;
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if (ArgVT == MVT::x86mmx)
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return false;
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unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
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Flags.setOrigAlign(OriginalAlignment);
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Args.push_back(ArgReg);
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ArgVals.push_back(ArgVal);
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ArgVTs.push_back(ArgVT);
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ArgFlags.push_back(Flags);
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}
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs,
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I->getParent()->getContext());
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// Allocate shadow area for Win64
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if (isWin64)
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CCInfo.AllocateStack(32, 8);
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CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_X86);
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = CCInfo.getNextStackOffset();
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// Issue CALLSEQ_START
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unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
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.addImm(NumBytes);
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// Process argument: walk the register/memloc assignments, inserting
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// copies / loads.
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SmallVector<unsigned, 4> RegArgs;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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unsigned Arg = Args[VA.getValNo()];
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EVT ArgVT = ArgVTs[VA.getValNo()];
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// Promote the value if needed.
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switch (VA.getLocInfo()) {
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case CCValAssign::Full: break;
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case CCValAssign::SExt: {
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assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
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"Unexpected extend");
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bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
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Arg, ArgVT, Arg);
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assert(Emitted && "Failed to emit a sext!"); (void)Emitted;
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ArgVT = VA.getLocVT();
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break;
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}
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case CCValAssign::ZExt: {
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assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
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"Unexpected extend");
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bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
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Arg, ArgVT, Arg);
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assert(Emitted && "Failed to emit a zext!"); (void)Emitted;
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ArgVT = VA.getLocVT();
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break;
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}
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case CCValAssign::AExt: {
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assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
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"Unexpected extend");
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bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
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Arg, ArgVT, Arg);
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if (!Emitted)
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Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
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Arg, ArgVT, Arg);
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if (!Emitted)
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Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
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Arg, ArgVT, Arg);
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assert(Emitted && "Failed to emit a aext!"); (void)Emitted;
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ArgVT = VA.getLocVT();
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break;
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}
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case CCValAssign::BCvt: {
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unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT(),
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ISD::BITCAST, Arg, /*TODO: Kill=*/false);
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assert(BC != 0 && "Failed to emit a bitcast!");
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Arg = BC;
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ArgVT = VA.getLocVT();
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break;
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}
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case CCValAssign::VExt:
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// VExt has not been implemented, so this should be impossible to reach
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// for now. However, fallback to Selection DAG isel once implemented.
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return false;
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case CCValAssign::Indirect:
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// FIXME: Indirect doesn't need extending, but fast-isel doesn't fully
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// support this.
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return false;
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case CCValAssign::FPExt:
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llvm_unreachable("Unexpected loc info!");
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}
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if (VA.isRegLoc()) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
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RegArgs.push_back(VA.getLocReg());
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} else {
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unsigned LocMemOffset = VA.getLocMemOffset();
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X86AddressMode AM;
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const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo*>(
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getTargetMachine()->getRegisterInfo());
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AM.Base.Reg = RegInfo->getStackRegister();
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AM.Disp = LocMemOffset;
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const Value *ArgVal = ArgVals[VA.getValNo()];
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ISD::ArgFlagsTy Flags = ArgFlags[VA.getValNo()];
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if (Flags.isByVal()) {
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X86AddressMode SrcAM;
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SrcAM.Base.Reg = Arg;
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bool Res = TryEmitSmallMemcpy(AM, SrcAM, Flags.getByValSize());
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assert(Res && "memcpy length already checked!"); (void)Res;
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} else if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal)) {
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// If this is a really simple value, emit this with the Value* version
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// of X86FastEmitStore. If it isn't simple, we don't want to do this,
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// as it can cause us to reevaluate the argument.
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if (!X86FastEmitStore(ArgVT, ArgVal, AM))
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return false;
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} else {
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if (!X86FastEmitStore(ArgVT, Arg, /*ValIsKill=*/false, AM))
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return false;
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}
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}
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}
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// ELF / PIC requires GOT in the EBX register before function calls via PLT
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// GOT pointer.
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if (Subtarget->isPICStyleGOT()) {
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unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), X86::EBX).addReg(Base);
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}
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if (Subtarget->is64Bit() && isVarArg && !isWin64) {
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// Count the number of XMM registers allocated.
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static const MCPhysReg XMMArgRegs[] = {
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X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
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X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
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};
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unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV8ri),
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X86::AL).addImm(NumXMMRegs);
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}
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// Issue the call.
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MachineInstrBuilder MIB;
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if (CalleeOp) {
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// Register-indirect call.
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unsigned CallOpc;
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if (Subtarget->is64Bit())
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CallOpc = X86::CALL64r;
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else
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CallOpc = X86::CALL32r;
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MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc))
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.addReg(CalleeOp);
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} else {
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// Direct call.
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assert(GV && "Not a direct call");
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unsigned CallOpc;
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if (Subtarget->is64Bit())
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CallOpc = X86::CALL64pcrel32;
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else
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CallOpc = X86::CALLpcrel32;
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||||||
|
|
||||||
// See if we need any target-specific flags on the GV operand.
|
|
||||||
unsigned char OpFlags = 0;
|
|
||||||
|
|
||||||
// On ELF targets, in both X86-64 and X86-32 mode, direct calls to
|
|
||||||
// external symbols most go through the PLT in PIC mode. If the symbol
|
|
||||||
// has hidden or protected visibility, or if it is static or local, then
|
|
||||||
// we don't need to use the PLT - we can directly call it.
|
|
||||||
if (Subtarget->isTargetELF() &&
|
|
||||||
TM.getRelocationModel() == Reloc::PIC_ &&
|
|
||||||
GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
|
|
||||||
OpFlags = X86II::MO_PLT;
|
|
||||||
} else if (Subtarget->isPICStyleStubAny() &&
|
|
||||||
(GV->isDeclaration() || GV->isWeakForLinker()) &&
|
|
||||||
(!Subtarget->getTargetTriple().isMacOSX() ||
|
|
||||||
Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
|
|
||||||
// PC-relative references to external symbols should go through $stub,
|
|
||||||
// unless we're building with the leopard linker or later, which
|
|
||||||
// automatically synthesizes these stubs.
|
|
||||||
OpFlags = X86II::MO_DARWIN_STUB;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc));
|
|
||||||
if (MemIntName)
|
|
||||||
MIB.addExternalSymbol(MemIntName, OpFlags);
|
|
||||||
else
|
|
||||||
MIB.addGlobalAddress(GV, 0, OpFlags);
|
|
||||||
}
|
|
||||||
|
|
||||||
// Add a register mask with the call-preserved registers.
|
|
||||||
// Proper defs for return values will be added by setPhysRegsDeadExcept().
|
|
||||||
MIB.addRegMask(TRI.getCallPreservedMask(CS.getCallingConv()));
|
|
||||||
|
|
||||||
// Add an implicit use GOT pointer in EBX.
|
|
||||||
if (Subtarget->isPICStyleGOT())
|
|
||||||
MIB.addReg(X86::EBX, RegState::Implicit);
|
|
||||||
|
|
||||||
if (Subtarget->is64Bit() && isVarArg && !isWin64)
|
|
||||||
MIB.addReg(X86::AL, RegState::Implicit);
|
|
||||||
|
|
||||||
// Add implicit physical register uses to the call.
|
|
||||||
for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
|
|
||||||
MIB.addReg(RegArgs[i], RegState::Implicit);
|
|
||||||
|
|
||||||
// Issue CALLSEQ_END
|
|
||||||
unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
|
|
||||||
unsigned NumBytesCallee = computeBytesPoppedByCallee(Subtarget, CC, &CS);
|
|
||||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
|
|
||||||
.addImm(NumBytes).addImm(NumBytesCallee);
|
|
||||||
|
|
||||||
// Build info for return calling conv lowering code.
|
|
||||||
// FIXME: This is practically a copy-paste from TargetLowering::LowerCallTo.
|
|
||||||
SmallVector<ISD::InputArg, 32> Ins;
|
|
||||||
SmallVector<EVT, 4> RetTys;
|
|
||||||
ComputeValueVTs(TLI, I->getType(), RetTys);
|
|
||||||
for (unsigned i = 0, e = RetTys.size(); i != e; ++i) {
|
|
||||||
EVT VT = RetTys[i];
|
|
||||||
MVT RegisterVT = TLI.getRegisterType(I->getParent()->getContext(), VT);
|
|
||||||
unsigned NumRegs = TLI.getNumRegisters(I->getParent()->getContext(), VT);
|
|
||||||
for (unsigned j = 0; j != NumRegs; ++j) {
|
|
||||||
ISD::InputArg MyFlags;
|
|
||||||
MyFlags.VT = RegisterVT;
|
|
||||||
MyFlags.Used = !CS.getInstruction()->use_empty();
|
|
||||||
if (CS.paramHasAttr(0, Attribute::SExt))
|
|
||||||
MyFlags.Flags.setSExt();
|
|
||||||
if (CS.paramHasAttr(0, Attribute::ZExt))
|
|
||||||
MyFlags.Flags.setZExt();
|
|
||||||
if (CS.paramHasAttr(0, Attribute::InReg))
|
|
||||||
MyFlags.Flags.setInReg();
|
|
||||||
Ins.push_back(MyFlags);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
// Now handle call return values.
|
|
||||||
SmallVector<unsigned, 4> UsedRegs;
|
|
||||||
SmallVector<CCValAssign, 16> RVLocs;
|
|
||||||
CCState CCRetInfo(CC, false, *FuncInfo.MF, TM, RVLocs,
|
|
||||||
I->getParent()->getContext());
|
|
||||||
unsigned ResultReg = FuncInfo.CreateRegs(I->getType());
|
|
||||||
CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86);
|
|
||||||
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
|
||||||
EVT CopyVT = RVLocs[i].getValVT();
|
|
||||||
unsigned CopyReg = ResultReg + i;
|
|
||||||
|
|
||||||
// If this is a call to a function that returns an fp value on the x87 fp
|
|
||||||
// stack, but where we prefer to use the value in xmm registers, copy it
|
|
||||||
// out as F80 and use a truncate to move it from fp stack reg to xmm reg.
|
|
||||||
if ((RVLocs[i].getLocReg() == X86::ST0 ||
|
|
||||||
RVLocs[i].getLocReg() == X86::ST1)) {
|
|
||||||
if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
|
|
||||||
CopyVT = MVT::f80;
|
|
||||||
CopyReg = createResultReg(&X86::RFP80RegClass);
|
|
||||||
}
|
|
||||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
||||||
TII.get(X86::FpPOP_RETVAL), CopyReg);
|
|
||||||
} else {
|
|
||||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
||||||
TII.get(TargetOpcode::COPY),
|
|
||||||
CopyReg).addReg(RVLocs[i].getLocReg());
|
|
||||||
UsedRegs.push_back(RVLocs[i].getLocReg());
|
|
||||||
}
|
|
||||||
|
|
||||||
if (CopyVT != RVLocs[i].getValVT()) {
|
|
||||||
// Round the F80 the right size, which also moves to the appropriate xmm
|
|
||||||
// register. This is accomplished by storing the F80 value in memory and
|
|
||||||
// then loading it back. Ewww...
|
|
||||||
EVT ResVT = RVLocs[i].getValVT();
|
|
||||||
unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
|
|
||||||
unsigned MemSize = ResVT.getSizeInBits()/8;
|
|
||||||
int FI = MFI.CreateStackObject(MemSize, MemSize, false);
|
|
||||||
addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
||||||
TII.get(Opc)), FI)
|
|
||||||
.addReg(CopyReg);
|
|
||||||
Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
|
|
||||||
addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
||||||
TII.get(Opc), ResultReg + i), FI);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (RVLocs.size())
|
|
||||||
UpdateValueMap(I, ResultReg, RVLocs.size());
|
|
||||||
|
|
||||||
// Set all unused physreg defs as dead.
|
|
||||||
static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
|
|
||||||
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
bool X86FastISel::FastLowerCall(CallLoweringInfo &CLI) {
|
bool X86FastISel::FastLowerCall(CallLoweringInfo &CLI) {
|
||||||
auto &OutVals = CLI.OutVals;
|
auto &OutVals = CLI.OutVals;
|
||||||
auto &OutFlags = CLI.OutFlags;
|
auto &OutFlags = CLI.OutFlags;
|
||||||
@@ -3516,8 +3056,6 @@ X86FastISel::TargetSelectInstruction(const Instruction *I) {
|
|||||||
return X86SelectZExt(I);
|
return X86SelectZExt(I);
|
||||||
case Instruction::Br:
|
case Instruction::Br:
|
||||||
return X86SelectBranch(I);
|
return X86SelectBranch(I);
|
||||||
case Instruction::Call:
|
|
||||||
return X86SelectCall(I);
|
|
||||||
case Instruction::LShr:
|
case Instruction::LShr:
|
||||||
case Instruction::AShr:
|
case Instruction::AShr:
|
||||||
case Instruction::Shl:
|
case Instruction::Shl:
|
||||||
|
|||||||
Reference in New Issue
Block a user