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ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
Add range checking to the immediate operands. Update tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135521 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3671,8 +3671,8 @@ def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
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imm:$CRm, imm:$opc2)]>;
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def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
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(outs GPR:$Rt),
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(ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm,
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i32imm:$opc2), []>;
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(ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
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imm0_7:$opc2), []>;
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def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
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(MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
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@ -3708,8 +3708,8 @@ def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
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imm:$CRm, imm:$opc2)]>;
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def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
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(outs GPR:$Rt),
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(ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm,
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i32imm:$opc2), []>;
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(ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
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imm0_7:$opc2), []>;
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def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
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imm:$CRm, imm:$opc2),
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@ -3389,13 +3389,12 @@ def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
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/* from coprocessor to ARM core register */
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def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
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(outs GPR:$Rt),
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(ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
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[]>;
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(outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
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c_imm:$CRm, imm0_7:$opc2), []>;
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def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
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(outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn,
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c_imm:$CRm, i32imm:$opc2), []>;
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(outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
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c_imm:$CRm, imm0_7:$opc2), []>;
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def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
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(t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
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@ -102,4 +102,18 @@
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@ Out of range immediate for MOVT
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movt r9, 0x10000
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ Out of range immediates for MRC/MRC2/MRRC/MRRC2
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mrc p14, #8, r1, c1, c2, #4
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mrc p14, #1, r1, c1, c2, #8
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mrc2 p14, #8, r1, c1, c2, #4
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mrc2 p14, #0, r1, c1, c2, #9
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mrrc p7, #16, r5, r4, c1
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mrrc2 p7, #17, r5, r4, c1
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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