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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-28 19:31:58 +00:00
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142626 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
parent
fe0748d696
commit
cd20c58e98
@ -4562,13 +4562,8 @@ def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
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// same and the assembly parser has no way to distinguish between them. The mask
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// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
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// the mask with the fields to be accessed in the special register.
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//
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// NOTE: There are separate versions of these instructions for M-class versus
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// AR-class processors. M-class processors can accept a wider range of
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// mask values than AR-class processors can.
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def MSRm : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
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"msr", "\t$mask, $Rn", []>,
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Requires<[IsMClass]> {
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def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
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"msr", "\t$mask, $Rn", []> {
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bits<5> mask;
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bits<4> Rn;
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@ -4581,9 +4576,8 @@ def MSRm : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
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let Inst{3-0} = Rn;
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}
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def MSRmi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
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"msr", "\t$mask, $a", []>,
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Requires<[IsMClass]> {
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def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
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"msr", "\t$mask, $a", []> {
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bits<5> mask;
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bits<12> a;
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@ -4595,38 +4589,6 @@ def MSRmi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
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let Inst{11-0} = a;
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}
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def MSRar : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
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"msr", "\t$mask, $Rn", []>,
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Requires<[IsARClass]> {
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bits<5> mask;
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bits<4> Rn;
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let Inst{23} = 0;
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let Inst{22} = 0;
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let Inst{21-20} = 0b10;
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let Inst{19-18} = mask{3-2};
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let Inst{17-16} = 0b00;
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let Inst{15-12} = 0b1111;
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let Inst{11-4} = 0b00000000;
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let Inst{3-0} = Rn;
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}
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def MSRari : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
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"msr", "\t$mask, $a", []>,
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Requires<[IsARClass]> {
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bits<5> mask;
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bits<12> a;
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let Inst{23} = 0;
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let Inst{22} = 0;
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let Inst{21-20} = 0b10;
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let Inst{19-18} = mask{3-2};
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let Inst{17-16} = 0b00;
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let Inst{15-12} = 0b1111;
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let Inst{11-0} = a;
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}
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//===----------------------------------------------------------------------===//
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// TLS Instructions
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//
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@ -928,15 +928,15 @@ Lforward:
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@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
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@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
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@ CHECK: msr APSR_nzcvqg, #5 @ encoding: [0x05,0xf0,0x2c,0xe3]
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@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
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@ CHECK: msr CPSR_c, #5 @ encoding: [0x05,0xf0,0x20,0xe3]
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@ CHECK: msr CPSR_x, #5 @ encoding: [0x05,0xf0,0x20,0xe3]
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@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
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@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
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@ CHECK: msr CPSR_fsx, #5 @ encoding: [0x05,0xf0,0x2c,0xe3]
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@ CHECK: msr SPSR_fc, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
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@ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2c,0xe3]
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@ CHECK: msr CPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2c,0xe3]
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@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3]
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@ CHECK: msr CPSR_c, #5 @ encoding: [0x05,0xf0,0x21,0xe3]
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@ CHECK: msr CPSR_x, #5 @ encoding: [0x05,0xf0,0x22,0xe3]
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@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3]
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@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3]
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@ CHECK: msr CPSR_fsx, #5 @ encoding: [0x05,0xf0,0x2e,0xe3]
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@ CHECK: msr SPSR_fc, #5 @ encoding: [0x05,0xf0,0x69,0xe3]
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@ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x6f,0xe3]
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@ CHECK: msr CPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2f,0xe3]
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msr apsr, r0
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msr apsr_g, r0
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@ -958,15 +958,15 @@ Lforward:
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@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
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@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
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@ CHECK: msr APSR_nzcvqg, r0 @ encoding: [0x00,0xf0,0x2c,0xe1]
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@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
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@ CHECK: msr CPSR_c, r0 @ encoding: [0x00,0xf0,0x20,0xe1]
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@ CHECK: msr CPSR_x, r0 @ encoding: [0x00,0xf0,0x20,0xe1]
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@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
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@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
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@ CHECK: msr CPSR_fsx, r0 @ encoding: [0x00,0xf0,0x2c,0xe1]
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@ CHECK: msr SPSR_fc, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
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@ CHECK: msr SPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2c,0xe1]
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@ CHECK: msr CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2c,0xe1]
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@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
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@ CHECK: msr CPSR_c, r0 @ encoding: [0x00,0xf0,0x21,0xe1]
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@ CHECK: msr CPSR_x, r0 @ encoding: [0x00,0xf0,0x22,0xe1]
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@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
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@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
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@ CHECK: msr CPSR_fsx, r0 @ encoding: [0x00,0xf0,0x2e,0xe1]
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@ CHECK: msr SPSR_fc, r0 @ encoding: [0x00,0xf0,0x69,0xe1]
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@ CHECK: msr SPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1]
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@ CHECK: msr CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1]
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@------------------------------------------------------------------------------
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@ MUL
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@ -161,6 +161,12 @@
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# CHECK: cpsie if, #10
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0xca 0x00 0x0a 0xf1
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# CHECK: msr CPSR_fc, r0
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0x00 0xf0 0x29 0xe1
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# CHECK: msrmi CPSR_c, #4043309056
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0xf1 0xf4 0x21 0x43
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# CHECK: rsbs r6, r7, r8
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0x08 0x60 0x77 0xe0
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@ -744,21 +744,65 @@
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# MSR
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#------------------------------------------------------------------------------
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# CHECK: msr CPSR_fc, #5
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# CHECK: msr APSR_g, #5
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# CHECK: msr APSR_nzcvq, #5
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# CHECK: msr APSR_nzcvq, #5
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# CHECK: msr APSR_nzcvqg, #5
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# CHECK: msr CPSR_fc, #5
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# CHECK: msr CPSR_c, #5
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# CHECK: msr CPSR_x, #5
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# CHECK: msr CPSR_xc, #5
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# CHECK: msr CPSR_fc, #5
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# CHECK: msr CPSR_fc, #5
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# CHECK: msr CPSR_fsx, #5
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# CHECK: msr SPSR_fc, #5
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# CHECK: msr SPSR_fsxc, #5
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# CHECK: msr CPSR_fsxc, #5
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0x05 0xf0 0x29 0xe3
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0x05 0xf0 0x24 0xe3
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0x05 0xf0 0x28 0xe3
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0x05 0xf0 0x28 0xe3
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0x05 0xf0 0x2c 0xe3
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0x05 0xf0 0x29 0xe3
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0x05 0xf0 0x21 0xe3
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0x05 0xf0 0x22 0xe3
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0x05 0xf0 0x29 0xe3
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0x05 0xf0 0x29 0xe3
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0x05 0xf0 0x2e 0xe3
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0x05 0xf0 0x69 0xe3
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0x05 0xf0 0x6f 0xe3
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0x05 0xf0 0x2f 0xe3
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# CHECK: msr CPSR_fc, r0
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# CHECK: msr APSR_g, r0
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# CHECK: msr APSR_nzcvq, r0
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# CHECK: msr APSR_nzcvq, r0
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# CHECK: msr APSR_nzcvqg, r0
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# CHECK: msr CPSR_fc, r0
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# CHECK: msr CPSR_c, r0
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# CHECK: msr CPSR_x, r0
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# CHECK: msr CPSR_xc, r0
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# CHECK: msr CPSR_fc, r0
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# CHECK: msr CPSR_fc, r0
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# CHECK: msr CPSR_fsx, r0
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# CHECK: msr SPSR_fc, r0
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# CHECK: msr SPSR_fsxc, r0
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# CHECK: msr CPSR_fsxc, r0
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0x00 0xf0 0x29 0xe1
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0x00 0xf0 0x24 0xe1
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0x00 0xf0 0x28 0xe1
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0x00 0xf0 0x28 0xe1
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0x00 0xf0 0x2c 0xe1
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0x00 0xf0 0x29 0xe1
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0x00 0xf0 0x21 0xe1
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0x00 0xf0 0x22 0xe1
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0x00 0xf0 0x29 0xe1
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0x00 0xf0 0x29 0xe1
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0x00 0xf0 0x2e 0xe1
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0x00 0xf0 0x69 0xe1
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0x00 0xf0 0x6f 0xe1
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0x00 0xf0 0x2f 0xe1
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#------------------------------------------------------------------------------
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# MUL
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