diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index d5f0c0a3b34..b9cbc83f217 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -4562,13 +4562,8 @@ def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, // same and the assembly parser has no way to distinguish between them. The mask // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains // the mask with the fields to be accessed in the special register. -// -// NOTE: There are separate versions of these instructions for M-class versus -// AR-class processors. M-class processors can accept a wider range of -// mask values than AR-class processors can. -def MSRm : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, - "msr", "\t$mask, $Rn", []>, - Requires<[IsMClass]> { +def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, + "msr", "\t$mask, $Rn", []> { bits<5> mask; bits<4> Rn; @@ -4581,9 +4576,8 @@ def MSRm : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, let Inst{3-0} = Rn; } -def MSRmi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary, - "msr", "\t$mask, $a", []>, - Requires<[IsMClass]> { +def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary, + "msr", "\t$mask, $a", []> { bits<5> mask; bits<12> a; @@ -4595,38 +4589,6 @@ def MSRmi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary, let Inst{11-0} = a; } -def MSRar : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, - "msr", "\t$mask, $Rn", []>, - Requires<[IsARClass]> { - bits<5> mask; - bits<4> Rn; - - let Inst{23} = 0; - let Inst{22} = 0; - let Inst{21-20} = 0b10; - let Inst{19-18} = mask{3-2}; - let Inst{17-16} = 0b00; - let Inst{15-12} = 0b1111; - let Inst{11-4} = 0b00000000; - let Inst{3-0} = Rn; -} - -def MSRari : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary, - "msr", "\t$mask, $a", []>, - Requires<[IsARClass]> { - bits<5> mask; - bits<12> a; - - let Inst{23} = 0; - let Inst{22} = 0; - let Inst{21-20} = 0b10; - let Inst{19-18} = mask{3-2}; - let Inst{17-16} = 0b00; - let Inst{15-12} = 0b1111; - let Inst{11-0} = a; -} - - //===----------------------------------------------------------------------===// // TLS Instructions // diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 66408820246..55d9f026195 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -928,15 +928,15 @@ Lforward: @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] @ CHECK: msr APSR_nzcvqg, #5 @ encoding: [0x05,0xf0,0x2c,0xe3] -@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x28,0xe3] -@ CHECK: msr CPSR_c, #5 @ encoding: [0x05,0xf0,0x20,0xe3] -@ CHECK: msr CPSR_x, #5 @ encoding: [0x05,0xf0,0x20,0xe3] -@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x28,0xe3] -@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x28,0xe3] -@ CHECK: msr CPSR_fsx, #5 @ encoding: [0x05,0xf0,0x2c,0xe3] -@ CHECK: msr SPSR_fc, #5 @ encoding: [0x05,0xf0,0x28,0xe3] -@ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2c,0xe3] -@ CHECK: msr CPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2c,0xe3] +@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr CPSR_c, #5 @ encoding: [0x05,0xf0,0x21,0xe3] +@ CHECK: msr CPSR_x, #5 @ encoding: [0x05,0xf0,0x22,0xe3] +@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr CPSR_fsx, #5 @ encoding: [0x05,0xf0,0x2e,0xe3] +@ CHECK: msr SPSR_fc, #5 @ encoding: [0x05,0xf0,0x69,0xe3] +@ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x6f,0xe3] +@ CHECK: msr CPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2f,0xe3] msr apsr, r0 msr apsr_g, r0 @@ -958,15 +958,15 @@ Lforward: @ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1] @ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1] @ CHECK: msr APSR_nzcvqg, r0 @ encoding: [0x00,0xf0,0x2c,0xe1] -@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x28,0xe1] -@ CHECK: msr CPSR_c, r0 @ encoding: [0x00,0xf0,0x20,0xe1] -@ CHECK: msr CPSR_x, r0 @ encoding: [0x00,0xf0,0x20,0xe1] -@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x28,0xe1] -@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x28,0xe1] -@ CHECK: msr CPSR_fsx, r0 @ encoding: [0x00,0xf0,0x2c,0xe1] -@ CHECK: msr SPSR_fc, r0 @ encoding: [0x00,0xf0,0x28,0xe1] -@ CHECK: msr SPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2c,0xe1] -@ CHECK: msr CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2c,0xe1] +@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr CPSR_c, r0 @ encoding: [0x00,0xf0,0x21,0xe1] +@ CHECK: msr CPSR_x, r0 @ encoding: [0x00,0xf0,0x22,0xe1] +@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr CPSR_fsx, r0 @ encoding: [0x00,0xf0,0x2e,0xe1] +@ CHECK: msr SPSR_fc, r0 @ encoding: [0x00,0xf0,0x69,0xe1] +@ CHECK: msr SPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1] +@ CHECK: msr CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1] @------------------------------------------------------------------------------ @ MUL diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 36627a34881..69a094dd681 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -161,6 +161,12 @@ # CHECK: cpsie if, #10 0xca 0x00 0x0a 0xf1 +# CHECK: msr CPSR_fc, r0 +0x00 0xf0 0x29 0xe1 + +# CHECK: msrmi CPSR_c, #4043309056 +0xf1 0xf4 0x21 0x43 + # CHECK: rsbs r6, r7, r8 0x08 0x60 0x77 0xe0 diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt index 06aa8f756da..fc7eda537ab 100644 --- a/test/MC/Disassembler/ARM/basic-arm-instructions.txt +++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt @@ -744,21 +744,65 @@ # MSR #------------------------------------------------------------------------------ +# CHECK: msr CPSR_fc, #5 +# CHECK: msr APSR_g, #5 +# CHECK: msr APSR_nzcvq, #5 +# CHECK: msr APSR_nzcvq, #5 +# CHECK: msr APSR_nzcvqg, #5 +# CHECK: msr CPSR_fc, #5 # CHECK: msr CPSR_c, #5 # CHECK: msr CPSR_x, #5 -# CHECK: msr CPSR_xc, #5 +# CHECK: msr CPSR_fc, #5 +# CHECK: msr CPSR_fc, #5 +# CHECK: msr CPSR_fsx, #5 +# CHECK: msr SPSR_fc, #5 +# CHECK: msr SPSR_fsxc, #5 +# CHECK: msr CPSR_fsxc, #5 +0x05 0xf0 0x29 0xe3 0x05 0xf0 0x24 0xe3 0x05 0xf0 0x28 0xe3 +0x05 0xf0 0x28 0xe3 0x05 0xf0 0x2c 0xe3 +0x05 0xf0 0x29 0xe3 +0x05 0xf0 0x21 0xe3 +0x05 0xf0 0x22 0xe3 +0x05 0xf0 0x29 0xe3 +0x05 0xf0 0x29 0xe3 +0x05 0xf0 0x2e 0xe3 +0x05 0xf0 0x69 0xe3 +0x05 0xf0 0x6f 0xe3 +0x05 0xf0 0x2f 0xe3 +# CHECK: msr CPSR_fc, r0 +# CHECK: msr APSR_g, r0 +# CHECK: msr APSR_nzcvq, r0 +# CHECK: msr APSR_nzcvq, r0 +# CHECK: msr APSR_nzcvqg, r0 +# CHECK: msr CPSR_fc, r0 # CHECK: msr CPSR_c, r0 # CHECK: msr CPSR_x, r0 -# CHECK: msr CPSR_xc, r0 +# CHECK: msr CPSR_fc, r0 +# CHECK: msr CPSR_fc, r0 +# CHECK: msr CPSR_fsx, r0 +# CHECK: msr SPSR_fc, r0 +# CHECK: msr SPSR_fsxc, r0 +# CHECK: msr CPSR_fsxc, r0 +0x00 0xf0 0x29 0xe1 0x00 0xf0 0x24 0xe1 0x00 0xf0 0x28 0xe1 +0x00 0xf0 0x28 0xe1 0x00 0xf0 0x2c 0xe1 +0x00 0xf0 0x29 0xe1 +0x00 0xf0 0x21 0xe1 +0x00 0xf0 0x22 0xe1 +0x00 0xf0 0x29 0xe1 +0x00 0xf0 0x29 0xe1 +0x00 0xf0 0x2e 0xe1 +0x00 0xf0 0x69 0xe1 +0x00 0xf0 0x6f 0xe1 +0x00 0xf0 0x2f 0xe1 #------------------------------------------------------------------------------ # MUL