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Eliminate data relocations by using NULL instead of global empty list.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29250 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Laskey 2006-07-21 21:15:20 +00:00
parent 60f09928a0
commit cd4317efcf
6 changed files with 50 additions and 37 deletions
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6
lib/CodeGen/LiveIntervalAnalysis.cpp
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@ -639,8 +639,10 @@ void LiveIntervals::computeIntervals()
DEBUG(std::cerr << getInstructionIndex(mi) << "\t" << *mi); DEBUG(std::cerr << getInstructionIndex(mi) << "\t" << *mi);
// handle implicit defs // handle implicit defs
for (const unsigned* id = tid.ImplicitDefs; *id; ++id) if (tid.ImplicitDefs) {
handleRegisterDef(mbb, mi, *id); for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
handleRegisterDef(mbb, mi, *id);
}
// handle explicit defs // handle explicit defs
for (int i = mi->getNumOperands() - 1; i >= 0; --i) { for (int i = mi->getNumOperands() - 1; i >= 0; --i) {

16
lib/CodeGen/LiveVariables.cpp
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@ -239,9 +239,11 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
NumOperandsToProcess = 1; NumOperandsToProcess = 1;
// Loop over implicit uses, using them. // Loop over implicit uses, using them.
for (const unsigned *ImplicitUses = MID.ImplicitUses; if (MID.ImplicitUses) {
*ImplicitUses; ++ImplicitUses) for (const unsigned *ImplicitUses = MID.ImplicitUses;
HandlePhysRegUse(*ImplicitUses, MI); *ImplicitUses; ++ImplicitUses)
HandlePhysRegUse(*ImplicitUses, MI);
}
// Process all explicit uses... // Process all explicit uses...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) { for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
@ -257,9 +259,11 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
} }
// Loop over implicit defs, defining them. // Loop over implicit defs, defining them.
for (const unsigned *ImplicitDefs = MID.ImplicitDefs; if (MID.ImplicitDefs) {
*ImplicitDefs; ++ImplicitDefs) for (const unsigned *ImplicitDefs = MID.ImplicitDefs;
HandlePhysRegDef(*ImplicitDefs, MI); *ImplicitDefs; ++ImplicitDefs)
HandlePhysRegDef(*ImplicitDefs, MI);
}
// Process all explicit defs... // Process all explicit defs...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) { for (unsigned i = 0; i != NumOperandsToProcess; ++i) {

34
lib/CodeGen/RegAllocLocal.cpp
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@ -525,9 +525,11 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
// Loop over the implicit uses, making sure that they are at the head of the // Loop over the implicit uses, making sure that they are at the head of the
// use order list, so they don't get reallocated. // use order list, so they don't get reallocated.
for (const unsigned *ImplicitUses = TID.ImplicitUses; if (TID.ImplicitUses) {
*ImplicitUses; ++ImplicitUses) for (const unsigned *ImplicitUses = TID.ImplicitUses;
MarkPhysRegRecentlyUsed(*ImplicitUses); *ImplicitUses; ++ImplicitUses)
MarkPhysRegRecentlyUsed(*ImplicitUses);
}
// Get the used operands into registers. This has the potential to spill // Get the used operands into registers. This has the potential to spill
// incoming values if we are out of registers. Note that we completely // incoming values if we are out of registers. Note that we completely
@ -587,19 +589,21 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
} }
// Loop over the implicit defs, spilling them as well. // Loop over the implicit defs, spilling them as well.
for (const unsigned *ImplicitDefs = TID.ImplicitDefs; if (TID.ImplicitDefs) {
*ImplicitDefs; ++ImplicitDefs) { for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
unsigned Reg = *ImplicitDefs; *ImplicitDefs; ++ImplicitDefs) {
spillPhysReg(MBB, MI, Reg, true); unsigned Reg = *ImplicitDefs;
PhysRegsUseOrder.push_back(Reg); spillPhysReg(MBB, MI, Reg, true);
PhysRegsUsed[Reg] = 0; // It is free and reserved now PhysRegsUseOrder.push_back(Reg);
PhysRegsEverUsed[Reg] = true; PhysRegsUsed[Reg] = 0; // It is free and reserved now
PhysRegsEverUsed[Reg] = true;
for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
*AliasSet; ++AliasSet) { *AliasSet; ++AliasSet) {
PhysRegsUseOrder.push_back(*AliasSet); PhysRegsUseOrder.push_back(*AliasSet);
PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
PhysRegsEverUsed[*AliasSet] = true; PhysRegsEverUsed[*AliasSet] = true;
}
} }
} }

14
lib/CodeGen/RegAllocSimple.cpp
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@ -166,12 +166,16 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
unsigned Opcode = MI->getOpcode(); unsigned Opcode = MI->getOpcode();
const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode); const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
const unsigned *Regs; const unsigned *Regs;
for (Regs = Desc.ImplicitUses; *Regs; ++Regs) if (Desc.ImplicitUses) {
RegsUsed[*Regs] = true; for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
RegsUsed[*Regs] = true;
}
for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) { if (Desc.ImplicitDefs) {
RegsUsed[*Regs] = true; for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
PhysRegsEverUsed[*Regs] = true; RegsUsed[*Regs] = true;
PhysRegsEverUsed[*Regs] = true;
}
} }
// Loop over uses, move from memory into registers. // Loop over uses, move from memory into registers.

10
lib/CodeGen/VirtRegMap.cpp
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@ -671,10 +671,12 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
// Loop over all of the implicit defs, clearing them from our available // Loop over all of the implicit defs, clearing them from our available
// sets. // sets.
for (const unsigned *ImpDef = TII->getImplicitDefs(MI.getOpcode()); const unsigned *ImpDef = TII->getImplicitDefs(MI.getOpcode());
*ImpDef; ++ImpDef) { if (ImpDef) {
PhysRegsUsed[*ImpDef] = true; for ( ; *ImpDef; ++ImpDef) {
Spills.ClobberPhysReg(*ImpDef); PhysRegsUsed[*ImpDef] = true;
Spills.ClobberPhysReg(*ImpDef);
}
} }
DEBUG(std::cerr << '\t' << MI); DEBUG(std::cerr << '\t' << MI);

7
utils/TableGen/InstrInfoEmitter.cpp
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@ -97,9 +97,6 @@ void InstrInfoEmitter::run(std::ostream &OS) {
const std::string &TargetName = Target.getName(); const std::string &TargetName = Target.getName();
Record *InstrInfo = Target.getInstructionSet(); Record *InstrInfo = Target.getInstructionSet();
// Emit empty implicit uses and defs lists
OS << "static const unsigned EmptyImpList[] = { 0 };\n";
// Keep track of all of the def lists we have emitted already. // Keep track of all of the def lists we have emitted already.
std::map<std::vector<Record*>, unsigned> EmittedLists; std::map<std::vector<Record*>, unsigned> EmittedLists;
unsigned ListNumber = 0; unsigned ListNumber = 0;
@ -239,13 +236,13 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
// Emit the implicit uses and defs lists... // Emit the implicit uses and defs lists...
std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
if (UseList.empty()) if (UseList.empty())
OS << "EmptyImpList, "; OS << "NULL, ";
else else
OS << "ImplicitList" << EmittedLists[UseList] << ", "; OS << "ImplicitList" << EmittedLists[UseList] << ", ";
std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
if (DefList.empty()) if (DefList.empty())
OS << "EmptyImpList, "; OS << "NULL, ";
else else
OS << "ImplicitList" << EmittedLists[DefList] << ", "; OS << "ImplicitList" << EmittedLists[DefList] << ", ";