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Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129531 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
2011-04-14 19:13:28 +00:00
parent b8295f7a0e
commit cd695fdac1
5 changed files with 74 additions and 4 deletions
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10
test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt Normal file
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@@ -0,0 +1,10 @@
# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=1934 Name=t2LDREXD Format=ARM_FORMAT_THUMBFRM(25)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 1| 0: 0: 1: 0| 1: 0: 0: 0| 1: 0: 0: 0| 0: 1: 1: 1| 1: 1: 1: 1|
# -------------------------------------------------------------------------------------------------
#
# if t == t2 then UNPREDICTABLE
0xd2 0xe8 0x7f 0x88

10
test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt Normal file
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@@ -0,0 +1,10 @@
# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 1: 0|
# -------------------------------------------------------------------------------------------------
#
# if d == n || d == t then UNPREDICTABLE
0xc2 0xe8 0x42 0x8f

10
test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt Normal file
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@@ -0,0 +1,10 @@
# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 0: 1: 1: 1| 1: 0: 0: 0| 0: 1: 1: 1| 1: 0: 0: 0|
# -------------------------------------------------------------------------------------------------
#
# if d == n || d == t || d == t2 then UNPREDICTABLE
mc-input.txt:1:1: warning: invalid instruction encoding

3
test/MC/Disassembler/ARM/thumb-tests.txt
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@@ -158,6 +158,9 @@
# CHECK: ldrex r8, [r2]
0x52 0xe8 0x00 0x8f
# CHECK: ldrexd r8, r9, [r2]
0xd2 0xe8 0x7f 0x89
# CHECK: strexd r1, r7, r8, [r2]
0xc2 0xe8 0x71 0x78