6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-15 23:31:37 +00:00
Code Issues Projects Releases Wiki Activity

Remove UseThumbBacktraces. Just check if subtarget is darwin.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73734 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-06-18 23:14:30 +00:00
parent bb4688a9cf
commit cd828618b8
5 changed files with 7 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -1483,7 +1483,7 @@ SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
unsigned FrameReg = (Subtarget->isThumb() || Subtarget->useThumbBacktraces())
unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
? ARM::R7 : ARM::R11;
SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
while (Depth--)

7
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -159,7 +159,7 @@ ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
const ARMSubtarget &sti)
: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
TII(tii), STI(sti),
FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
}
static inline
@ -1687,9 +1687,8 @@ unsigned ARMRegisterInfo::getRARegister() const {
unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
if (STI.isTargetDarwin() || hasFP(MF))
return (STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11;
else
return ARM::SP;
return FramePtr;
return ARM::SP;
}
unsigned ARMRegisterInfo::getEHExceptionRegister() const {

4
lib/Target/ARM/ARMRegisterInfo.td
View File

@ -134,7 +134,7 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
GPRClass::allocation_order_begin(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
if (Subtarget.useThumbBacktraces()) {
if (Subtarget.isTargetDarwin()) {
if (Subtarget.isR9Reserved())
return ARM_GPR_AO_4;
else
@ -154,7 +154,7 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
GPRClass::iterator I;
if (Subtarget.useThumbBacktraces()) {
if (Subtarget.isTargetDarwin()) {
if (Subtarget.isR9Reserved()) {
I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
} else {

5
lib/Target/ARM/ARMSubtarget.cpp
View File

@ -24,7 +24,6 @@ ARMSubtarget::ARMSubtarget(const Module &M, const std::string &FS,
, ARMFPUType(None)
, IsThumb(isThumb)
, ThumbMode(Thumb1)
, UseThumbBacktraces(false)
, IsR9Reserved(false)
, stackAlignment(4)
, CPUString("generic")
@ -83,8 +82,6 @@ ARMSubtarget::ARMSubtarget(const Module &M, const std::string &FS,
if (isAAPCS_ABI())
stackAlignment = 8;
if (isTargetDarwin()) {
UseThumbBacktraces = true;
if (isTargetDarwin())
IsR9Reserved = true;
}
}

4
lib/Target/ARM/ARMSubtarget.h
View File

@ -48,9 +48,6 @@ protected:
/// ThumbMode - Indicates supported Thumb version.
ThumbTypeEnum ThumbMode;
/// UseThumbBacktraces - True if we use thumb style backtraces.
bool UseThumbBacktraces;
/// IsR9Reserved - True if R9 is a not available as general purpose register.
bool IsR9Reserved;
@ -109,7 +106,6 @@ protected:
bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
bool hasThumb2() const { return IsThumb && (ThumbMode >= Thumb2); }
bool useThumbBacktraces() const { return UseThumbBacktraces; }
bool isR9Reserved() const { return IsR9Reserved; }
const std::string & getCPUString() const { return CPUString; }