From cdce03426d357164c1d15154e251d22e02cc8bc1 Mon Sep 17 00:00:00 2001 From: Elena Demikhovsky Date: Thu, 22 Jan 2015 09:39:08 +0000 Subject: [PATCH] Fixed a bug in narrowing store operation. Type MVT::i1 became legal in KNL, but store operation can't be narrowed to this type, since the size of VT (1 bit) is not equal to its actual store size(8 bits). Added a test provided by David (dag@cray.com) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226805 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 7 +++++-- test/CodeGen/X86/i1narrowfail.ll | 10 ++++++++++ 2 files changed, 15 insertions(+), 2 deletions(-) create mode 100644 test/CodeGen/X86/i1narrowfail.ll diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 849508891d3..4a9ae200663 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -9497,9 +9497,12 @@ SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; unsigned NewBW = NextPowerOf2(MSB - ShAmt); EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); + // The narowwing should be profitable, the load/store operation should be + // legal (or custom) and the store size should be equal to the NewVT width. while (NewBW < BitWidth && - !(TLI.isOperationLegalOrCustom(Opc, NewVT) && - TLI.isNarrowingProfitable(VT, NewVT))) { + (NewVT.getStoreSizeInBits() != NewBW || + !TLI.isOperationLegalOrCustom(Opc, NewVT) || + !TLI.isNarrowingProfitable(VT, NewVT))) { NewBW = NextPowerOf2(NewBW); NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); } diff --git a/test/CodeGen/X86/i1narrowfail.ll b/test/CodeGen/X86/i1narrowfail.ll new file mode 100644 index 00000000000..e280f3cff51 --- /dev/null +++ b/test/CodeGen/X86/i1narrowfail.ll @@ -0,0 +1,10 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s + +; CHECK-LABEL: @foo +; CHECK: orb $16 +define void @foo(i64* %ptr) { + %r11 = load i64* %ptr, align 8 + %r12 = or i64 16, %r11 + store i64 %r12, i64* %ptr, align 8 + ret void +}