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AArch64: Fix a bug about disassembling post-index load single element to 4 vectors

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195903 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hao Liu
2013-11-28 01:07:45 +00:00
parent 18a777a09a
commit cdd732cdd3
2 changed files with 7 additions and 5 deletions
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8
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
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@@ -1342,13 +1342,13 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: {
switch (Opc) {
case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
TransferBytes = 3; break;
TransferBytes = 4; break;
case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register:
TransferBytes = 6; break;
TransferBytes = 8; break;
case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register:
TransferBytes = 12; break;
TransferBytes = 16; break;
case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register:
TransferBytes = 24; break;
TransferBytes = 32; break;
}
IsLoad = true;
NumVecs = 4;