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[Mips][Disassembler]When disassembler meets load/store from coprocessor 2 instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226652 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vladimir Medic
2015-01-21 10:47:36 +00:00
parent 74670deb21
commit cde587f359
8 changed files with 39 additions and 8 deletions
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21
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
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@@ -304,6 +304,10 @@ static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
@@ -1354,6 +1358,23 @@ static DecodeStatus DecodeFMem3(MCInst &Inst,
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<11>(Insn & 0x07ff);
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
unsigned Base = fieldFromInstruction(Insn, 11, 5);
Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::CreateReg(Reg));
Inst.addOperand(MCOperand::CreateReg(Base));
Inst.addOperand(MCOperand::CreateImm(Offset));
return MCDisassembler::Success;
}
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,

2
lib/Target/Mips/Mips32r6InstrInfo.td
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@@ -561,6 +561,7 @@ class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> {
string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = []; list<dag> Pattern = [];
bit mayLoad = 1; bit mayLoad = 1;
string DecoderMethod = "DecodeFMemCop2R6";
} }
class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd>; class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd>;
@@ -572,6 +573,7 @@ class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> {
string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = []; list<dag> Pattern = [];
bit mayStore = 1; bit mayStore = 1;
string DecoderMethod = "DecodeFMemCop2R6";
} }
class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd>; class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd>;

4
test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
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@@ -138,3 +138,7 @@
0x33 0xfe 0x1d 0x02 # CHECK: tltu $16, $sp, 1016 0x33 0xfe 0x1d 0x02 # CHECK: tltu $16, $sp, 1016
0x36 0x00 0xd1 0x00 # CHECK: tne $6, $17 0x36 0x00 0xd1 0x00 # CHECK: tne $6, $17
0x76 0xdd 0xe8 0x00 # CHECK: tne $7, $8, 885 0x76 0xdd 0xe8 0x00 # CHECK: tne $7, $8, 885
0x43 0x0d 0xc8 0x49 # CHECK: ldc2 $8, -701($1)
0xb7 0x34 0x52 0x49 # CHECK: lwc2 $18, -841($6)
0x75 0x92 0xf4 0x49 # CHECK: sdc2 $20, 629($18)
0x30 0x81 0x79 0x49 # CHECK: swc2 $25, 304($16)

4
test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
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@@ -138,3 +138,7 @@
0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016
0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17 0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17
0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885 0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885
0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1)
0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6)
0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16)

4
test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt
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@@ -17,7 +17,3 @@
0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256 0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5) 0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1)
0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6)
0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16)

4
test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
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@@ -156,3 +156,7 @@
0x33 0xfe 0x1d 0x02 # CHECK: tltu $16, $sp, 1016 0x33 0xfe 0x1d 0x02 # CHECK: tltu $16, $sp, 1016
0x36 0x00 0xd1 0x00 # CHECK: tne $6, $17 0x36 0x00 0xd1 0x00 # CHECK: tne $6, $17
0x76 0xdd 0xe8 0x00 # CHECK: tne $7, $8, 885 0x76 0xdd 0xe8 0x00 # CHECK: tne $7, $8, 885
0x43 0x0d 0xc8 0x49 # CHECK: ldc2 $8, -701($1)
0xb7 0x34 0x52 0x49 # CHECK: lwc2 $18, -841($6)
0x75 0x92 0xf4 0x49 # CHECK: sdc2 $20, 629($18)
0x30 0x81 0x79 0x49 # CHECK: swc2 $25, 304($16)

4
test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
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@@ -156,3 +156,7 @@
0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016
0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17 0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17
0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885 0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885
0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1)
0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6)
0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16)

4
test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt
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@@ -17,10 +17,6 @@
0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256 0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5) 0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1)
0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6)
0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16)
0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079 0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079
0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943 0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025 0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025