6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-21 18:24:23 +00:00
Code Issues Projects Releases Wiki Activity

Add FPTrunc, fix some bugs where I forgot to update the value map.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113533 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
2010-09-09 20:26:31 +00:00
parent 547462b98c
commit ce07b5458d
1 changed files with 28 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
lib/Target/ARM/ARMFastISel.cpp
View File

@ -115,6 +115,7 @@ class ARMFastISel : public FastISel {
virtual bool ARMSelectBranch(const Instruction *I); virtual bool ARMSelectBranch(const Instruction *I);
virtual bool ARMSelectCmp(const Instruction *I); virtual bool ARMSelectCmp(const Instruction *I);
virtual bool ARMSelectFPExt(const Instruction *I); virtual bool ARMSelectFPExt(const Instruction *I);
virtual bool ARMSelectFPTrunc(const Instruction *I);
virtual bool ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode); virtual bool ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
virtual bool ARMSelectSIToFP(const Instruction *I); virtual bool ARMSelectSIToFP(const Instruction *I);
virtual bool ARMSelectFPToSI(const Instruction *I); virtual bool ARMSelectFPToSI(const Instruction *I);
@ -545,7 +546,6 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(Opc), ResultReg) TII.get(Opc), ResultReg)
.addReg(Reg).addReg(0).addImm(Offset)); .addReg(Reg).addReg(0).addImm(Offset));
return true; return true;
} }
@ -630,7 +630,6 @@ bool ARMFastISel::ARMSelectStore(const Instruction *I) {
if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false; if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false;
return false; return false;
} }
bool ARMFastISel::ARMSelectLoad(const Instruction *I) { bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
@ -720,6 +719,8 @@ bool ARMFastISel::ARMSelectCmp(const Instruction *I) {
if (isFloat) if (isFloat)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::FMSTAT))); TII.get(ARM::FMSTAT)));
// TODO: How to update the value map when there's no result reg?
return true; return true;
} }
@ -736,6 +737,26 @@ bool ARMFastISel::ARMSelectFPExt(const Instruction *I) {
unsigned Result = createResultReg(ARM::DPRRegisterClass); unsigned Result = createResultReg(ARM::DPRRegisterClass);
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::VCVTSD), Result)
.addReg(Op));
UpdateValueMap(I, Result);
return true;
}
bool ARMFastISel::ARMSelectFPTrunc(const Instruction *I) {
// Make sure we have VFP and that we're truncating double to float.
if (!Subtarget->hasVFP2()) return false;
Value *V = I->getOperand(0);
if (!I->getType()->isFloatTy() ||
!V->getType()->isDoubleTy()) return false;
unsigned Op = getRegForValue(V);
if (Op == 0) return false;
unsigned Result = createResultReg(ARM::SPRRegisterClass);
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::VCVTDS), Result) TII.get(ARM::VCVTDS), Result)
.addReg(Op)); .addReg(Op));
@ -764,6 +785,7 @@ bool ARMFastISel::ARMSelectSIToFP(const Instruction *I) {
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
ResultReg) ResultReg)
.addReg(Op)); .addReg(Op));
UpdateValueMap(I, ResultReg);
return true; return true;
} }
@ -789,6 +811,7 @@ bool ARMFastISel::ARMSelectFPToSI(const Instruction *I) {
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
ResultReg) ResultReg)
.addReg(Op)); .addReg(Op));
UpdateValueMap(I, ResultReg);
return true; return true;
} }
@ -829,6 +852,7 @@ bool ARMFastISel::ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(Opc), ResultReg) TII.get(Opc), ResultReg)
.addReg(Op1).addReg(Op2)); .addReg(Op1).addReg(Op2));
UpdateValueMap(I, ResultReg);
return true; return true;
} }
@ -849,6 +873,8 @@ bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
return ARMSelectCmp(I); return ARMSelectCmp(I);
case Instruction::FPExt: case Instruction::FPExt:
return ARMSelectFPExt(I); return ARMSelectFPExt(I);
case Instruction::FPTrunc:
return ARMSelectFPTrunc(I);
case Instruction::SIToFP: case Instruction::SIToFP:
return ARMSelectSIToFP(I); return ARMSelectSIToFP(I);
case Instruction::FPToSI: case Instruction::FPToSI: